XC5VLX220T-2FF1738C Xilinx Inc, XC5VLX220T-2FF1738C Datasheet - Page 216
![IC FPGA VIRTEX-5 220K 1738FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX220T-2FF1738C
Manufacturer Part Number
XC5VLX220T-2FF1738C
Description
IC FPGA VIRTEX-5 220K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-2FF1738C
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7815168
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
For Use With
HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number:
XC5VLX220T-2FF1738C
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Xilinx Inc
Quantity:
10 000
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Chapter 5: Configurable Logic Blocks (CLBs)
216
Port Signals
logic in terms of performance and area. It also automatically uses and connects this
function properly.
Sum Outputs – O[3:0]
The sum outputs provide the final result of the addition/subtraction.
Carry Outputs – CO[3:0]
The carry outputs provide the carry out for each bit. A longer carry chain can be created if
CO[3] is connected to CI input of another CARRY4 primitive.
Data Inputs – DI[3:0]
The data inputs are used as “generate” signals to the carry lookahead logic. The “generate”
signals are sourced from LUT outputs.
Select Inputs – S[3:0]
The select inputs are used as “propagate” signals to the carry lookahead logic. The
“propagate” signals are sourced from LUT outputs.
Carry Initialize – CYINIT
The carry initialize input is used to select the first bit in a carry chain. The value for this pin
is either 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry bit).
Carry In – CI
The carry in input is used to cascade slices to form longer carry chain. To create a longer
carry chain, the CO[3] output of another CARRY4 is simply connected to this pin.
Figure 5-24, page 199
www.xilinx.com
illustrates the CARRY4 block diagram.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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