XC5VLX220-2FF1760I Xilinx Inc, XC5VLX220-2FF1760I Datasheet - Page 341
![IC FPGA VIRTEX-5 220K 1760FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX220-2FF1760I
Manufacturer Part Number
XC5VLX220-2FF1760I
Description
IC FPGA VIRTEX-5 220K 1760FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220-2FF1760I
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7077888
Number Of I /o
800
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1760-BBGA, FCBGA
For Use With
HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220-2FF1760I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 7-18
Figure 7-18: Instantiate IDELAYCTRL Without LOC Constraints - RDY Unconnected
2.
X-Ref Target - Figure 7-19
Figure 7-19: Instantiate IDELAYCTRL Without LOC Constraints - RDY Connected
REFCLK
When RDY port is connected, an AND gate of width equal to the number of clock
regions is instantiated and the RDY output ports from the instantiated and replicated
IDELAYCTRL instances are connected to the inputs of the AND gate. The tools assign
the signal name connected to the RDY port of the instantiated IDELAYCTRL instance
to the output of the AND gate.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints with the RDY port connected are provided in the Libraries
Guide.
The resulting circuitry after instantiating the IDELAYCTRL components is illustrated
in
REFCLK
RST
Figure
RST
7-19.
.
.
.
.
.
.
.
.
.
www.xilinx.com
.
.
.
all IDELAYCTRL
all IDELAYCTRL
Replicated for
Instantiated by user
REFCLK
RST
REFCLK
RST
REFCLK
RST
Replicated for
Instantiated by user
REFCLK
RST
REFCLK
RST
REFCLK
RST
IDELAYCTRL
IDELAYCTRL
IDELAYCTRL
sites
IDELAYCTRL
IDELAYCTRL
IDELAYCTRL
sites
.
.
.
.
.
.
RDY
RDY
RDY
Input/Output Delay Element (IODELAY)
RDY
RDY
RDY
Auto-generated by
mapper tool
RDY signal ignored
Auto-generated by
mapper tool
ug190_7_13_041206
ug190_7_14_041306
RDY
341
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