XC4005A-6PC84C Xilinx Inc, XC4005A-6PC84C Datasheet - Page 8

• Manufacturer Part Number: XC4005A-6PC84C
• Description: IC LOGIC CL ARRAY 5000GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005A-6PC84C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 61
• Number Of Gates: 5000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1051

XC4000, XC4000A, XC4000H Logic Cell Array Families
pass through a global buffer before arriving at the IOB. This
eliminates the possibility of a data hold-time requirement
at the external pin. The I1 and I2 signals that exit the block
can each carry either the direct or registered input signal.
Output signals can be inverted or not inverted, and can
pass directly to the pad or be stored in an edge-triggered
flip-flop. Optionally, an output enable signal can be used to
place the output buffer in a high-impedance state, imple-
menting 3-state outputs or bidirectional I/O. Under con-
figuration control, the output (OUT) and output enable
(OE) signals can be inverted, and the slew rate of the
output buffer can be reduced to minimize power bus
transients when switching non-critical signals. Each
XC4000-families output buffer is capable of sinking 12 mA;
two adjacent output buffers can be wire-ANDed externally
to sink up to 24 mA. In the XC4000A and XC4000H
families, each output buffer can sink 24 mA.
There are a number of other programmable options in the
IOB. Programmable pull-up and pull-down resistors are
useful for tying unused pins to V
power consumption. Separate clock signals are provided
for the input and output registers; these clocks can be
inverted, generating either falling-edge or rising-edge trig-
gered flip-flops. As is the case with the CLB registers, a
global set/reset signal can be used to set or clear the input
and output registers whenever the RESET net is active.
Embedded logic attached to the IOBs contains test struc-
tures compatible with IEEE Standard 1149.1 for boundary-
scan testing, permitting easy chip and board-level testing.
Figure 5. XC4000 and XC4000A Families
Output
Clock
Clock
Input
Out
OE
I
I
1
2
Input/Output Block
D Q
Q
Latch
Flop/
Flip-
Flop
Flip-
D
Slew Rate
Delay
Control
CC
or ground to minimize
Output
Buffer
Buffer
Input
Pull-Down
Passive
Pull-Up/
X6073
Pad
2-14
Programmable Interconnect
All internal connections are composed of metal segments
with programmable switching points to implement the
desired routing. An abundance of different routing re-
sources is provided to achieve efficient automated routing.
The number of routing channels is scaled to the size of the
array; i.e., it increases with array size.
In previous generations of LCAs, the logic-block inputs
were located on the top, left, and bottom of the block;
outputs exited the block on the right, favoring left-to-right
data flow through the device. For the third-generation
family, the CLB inputs and outputs are distributed on all
four sides of the block, providing additional routing flexibil-
ity (Figure 6). In general, the entire architecture is more
symmetrical and regular than that of earlier generations,
and is more suited to well-established placement and
routing algorithms developed for conventional mask- pro-
grammed gate-array design.
There are three main types of interconnect, distinguished
by the relative length of their segments: single-length lines,
double-length lines, and Longlines. Note: The number of
routing channels shown in Figures 6 and 9 are for illustra-
tion purposes only; the actual number of routing channels
varies with array size. The routing scheme was designed
for minimum resistance and capacitance of the average
routing path, resulting in significant performance improve-
ments.
The single-length lines are a grid of horizontal and vertical
lines that intersect at a Switch Matrix between each block.
Figure 6 illustrates the single-length interconnect lines
Figure 6. Typical CLB Connections to Adjacent
Switch
Switch
Matrix
Matrix
Single-Length Lines
G1
C1
K
F1
X
XQ
F4
C4
F2
CLB
G4
C2
YQ
G2
G3
C3
F3
Y
Switch
Switch
Matrix
Matrix
X3242