XC3090-100PP175C Xilinx Inc, XC3090-100PP175C Datasheet - Page 4
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XC3090-100PP175C
Manufacturer Part Number
XC3090-100PP175C
Description
IC LOGIC CL ARRAY 9000GAT 175PPG
Manufacturer
Xilinx Inc
Series
XC3000r
Datasheet
1.XC3090-100PQ208C.pdf
(8 pages)
Specifications of XC3090-100PP175C
Number Of Labs/clbs
320
Total Ram Bits
64160
Number Of I /o
144
Number Of Gates
6000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
175-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1031
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
XC3000 Logic Cell Array Family
CLB Switching Characteristic Guidelines
Buffer (Internal) Switching Characteristic Guidelines
* Timing is based on the XC3042, for other devices see XACT timing calculator.
Global and Alternate Clock Distribution*
TBUF driving a Horizontal Longline (L.L.)*
BIDI
Description
Either: Normal IOB input pad through clock buffer
Or:
I to L.L. while T is Low (buffer active)
T to L.L. active and valid with single pull-up resistor
T to L.L. active and valid with pair of pull-up resistors
T to L.L. High with single pull-up resistor
T to L.L. High with pair of pull-up resistors
Bidirectional buffer delay
to any CLB or IOB clock input
Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
CLB Output (X, Y)
(Combinatorial)
(Enable Clock)
(Reset Direct)
(A,B,C,D,E)
CLB Output
CLB Output
CLB Clock
(Flip-Flop)
(Flip-Flop)
CLB Input
CLB Input
CLB Input
CLB Input
(Direct In)
9 T
RIO
12 T
1 T
2 T
6 T
13 T
4 T
ILO
CL
2-156
ICK
Speed Grade
ECCK
RPW
DICK
Symbol
T
T
T
T
T
T
T
T
PID
PIDC
IO
ON
ON
PUS
PUF
BIDI
7 T
3 T
5 T
CKEC
CKI
8 T
CKDI
11 T
Max
11.0
12.0
24.0
17.0
-70
CKO
8.0
6.5
5.0
2.0
CH
10.0
11.0
22.0
15.0
-100
Max
7.5
6.0
4.7
1.8
X5388
10.0
17.0
12.0
-125
Max
7.0
5.7
4.5
9.0
1.7
Units
ns
ns
ns
ns
ns
ns
ns
ns