XC4010-5PQ208C Xilinx Inc, XC4010-5PQ208C Datasheet - Page 27

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XC4010-5PQ208C

Manufacturer Part Number
XC4010-5PQ208C
Description
IC LOGIC CL ARRAY 10K GAT 208PQ
Manufacturer
Xilinx Inc
Series
XC4000r
Datasheet

Specifications of XC4010-5PQ208C

Number Of Logic Elements/cells
950
Number Of Labs/clbs
400
Total Ram Bits
12800
Number Of I /o
160
Number Of Gates
10000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Case
QFP208
Dc
96+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1071

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0
externally, the device determines its configuration mode
by capturing its status inputs, and is ready to start the
configuration process. A master device waits an additional
Notes: 1. At power-up, V
Master Serial Mode Programming Switching Characteristics
CCLK
Serial Data In
Serial DOUT
2. Configuration can be controlled by holding INIT Low with or until after the INIT of all daisy-chain slave mode devices
3. Master-serial-mode timing is based on testing in slave mode.
(Output)
(Output)
PROGRAM Low until V
is High.
CCLK
n – 3
CC
must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling
Description
Data In setup
Data In hold
1
CC
T
is valid.
DSCK
n
n – 2
2 T
1
2
2-33
CKDS
Symbol
n + 1
up to 250 s to make sure that all slaves in the potential
daisy-chain have seen INIT being High.
T
T
DSCK
CKDS
n – 1
Min
20
0
n + 2
Max
n
Units
ns
ns
X3223

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