XC5206-6PQ160C Xilinx Inc, XC5206-6PQ160C Datasheet - Page 47
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XC5206-6PQ160C
Manufacturer Part Number
XC5206-6PQ160C
Description
IC FPGA 196 CLB'S 160-PQFP
Manufacturer
Xilinx Inc
Series
XC5200r
Datasheet
1.XC5206-5PQ208C.pdf
(73 pages)
Specifications of XC5206-6PQ160C
Number Of Logic Elements/cells
784
Number Of Labs/clbs
196
Number Of I /o
133
Number Of Gates
10000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-BQFP
Case
QFP160
Dc
96+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
122-1141
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5206-6PQ160C
Manufacturer:
XILINX
Quantity:
688
Company:
Part Number:
XC5206-6PQ160C
Manufacturer:
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Quantity:
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XC5200 CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
November 5, 1998 (Version 5.2)
Combinatorial Delays
Carry Delays
Sequential Delays
Set-up Time Before Clock (CK)
Hold Times After Clock (CK)
Clock Widths
Reset Delays
Global Reset Delays
Note:
F inputs to X output
F inputs via transparent latch to Q
DI inputs to DO output (Logic-Cell
Feedthrough)
F inputs via F5_MUX to DO output
Incremental delay per bit
Carry-in overhead from DI
Carry-in overhead from F
Carry-out overhead to DO
Clock (CK) to out (Q) (Flip-Flop)
Gate (Latch enable) going active to out (Q)
F inputs
F inputs via F5_MUX
DI input
CE input
F inputs
F inputs via F5_MUX
DI input
CE input
Clock High Time
Clock Low Time
Toggle Frequency (MHz) (Note 3)
Width (High)
Delay from CLR to Q (Flip-Flop)
Delay from CLR to Q (Latch)
Width (High)
Delay from internal GR to Q
1. The CLB K to Q output delay (T
2. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.
3. Maximum flip-flop toggle rate for export control purposes.
Data In hold-time requirement (T
R
Description
Product Obsolete or Under Obsolescence
CKO
CKDI
Speed Grade
) of any CLB, plus the shortest possible interconnect delay, is always longer than the
) of any CLB on the same die.
Symbol
T
T
T
T
T
T
F
T
T
T
T
T
T
T
T
T
T
T
GCLRW
T
T
T
T
T
T
T
T
CLRW
GCLR
CKMI
CLRL
CYDI
MICK
DICK
EICK
CKDI
CKEI
TOG
CYL
CYO
CKO
CLR
IMO
ITO
IDO
ICK
CKI
ILO
CY
GO
CH
CL
XC5200 Series Field Programmable Gate Arrays
(ns)
Min
2.3
3.8
0.8
1.6
6.0
6.0
6.0
6.0
0
0
0
0
-6
Max
14.7
(ns)
5.6
8.0
4.3
7.2
0.7
1.8
3.7
4.0
5.8
9.2
7.7
6.5
83
(ns)
Min
1.8
3.0
0.5
1.2
6.0
6.0
6.0
6.0
0
0
0
0
-5
Max
12.1
(ns)
4.6
6.6
3.5
5.8
0.6
1.6
3.2
3.2
4.9
7.4
6.3
5.2
83
(ns)
Min
1.4
2.5
0.4
0.9
6.0
6.0
6.0
6.0
0
0
0
0
-4
Max
(ns)
3.8
5.4
2.8
5.0
0.5
1.5
2.9
2.5
4.0
5.9
5.1
4.2
9.1
83
(ns)
Min
1.3
2.4
0.4
0.9
6.0
6.0
6.0
6.0
0
0
0
0
-3
Max
(ns)
7-129
3.0
4.3
2.4
4.3
0.5
1.4
2.4
2.1
4.0
5.5
4.0
3.0
8.0
83
7