XC3090L-8PC84I Xilinx Inc, XC3090L-8PC84I Datasheet - Page 13

• Manufacturer Part Number: XC3090L-8PC84I
• Description: IC FPGA 3.3V I-TEMP 84-PLCC
• Manufacturer: Xilinx Inc
• Series: XC3000A/Lr

Specifications of XC3090L-8PC84I

• Number Of Labs/clbs: 320
• Total Ram Bits: 64160
• Number Of I /o: 70
• Number Of Gates: 6000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

Longlines
The Longlines bypass the switch matrices and are intended
primarily for signals that must travel a long distance, or
must have minimum skew among multiple destinations.
Longlines, shown in
tally the height or width of the interconnect area. Each inter-
connection column has three vertical Longlines, and each
interconnection row has two horizontal Longlines. Two
additional Longlines are located adjacent to the outer sets
of switching matrices. In devices larger than the XC3020A
and XC3120A FPGAs, two vertical Longlines in each col-
November 9, 1998 (Version 3.1)
Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.
R
Figure
Product Obsolete or Under Obsolescence
14, run vertically and horizon-
XC3000 Series Field Programmable Gate Arrays
umn are connectable half-length lines. On the XC3020A
and XC3120A FPGAs, only the outer Longlines are con-
nectable half-length lines.
Longlines can be driven by a logic block or IOB output on a
column-by-column basis. This capability provides a com-
mon low skew control or clock line within each column of
logic blocks. Interconnections of these Longlines are
shown in
input to a Longline and are enabled automatically by the
development system when a connection is made.
Figure
15. Isolation buffers are provided at each
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