XC4036XL-3HQ208C Xilinx Inc, XC4036XL-3HQ208C Datasheet
XC4036XL-3HQ208C
Manufacturer Part Number
XC4036XL-3HQ208C
Description
IC FPGA C-TEMP 3.3V 3SPD 208HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4036XL-3HQ208C.pdf
(68 pages)
Specifications of XC4036XL-3HQ208C
Number Of Logic Elements/cells
3078
Number Of Labs/clbs
1296
Total Ram Bits
41472
Number Of I /o
160
Number Of Gates
36000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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May 14, 1999 (Version 1.6)
XC4000E and XC4000X Series
Features
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx web site at
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
• System featured Field-Programmable Gate Arrays
• System Performance beyond 80 MHz
• Flexible Array Architecture
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
• Configured by Loading Binary File
• Read Back Capability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
May 14, 1999 (Version 1.6)
- SelectRAM
- Fully PCI compliant (speed grades -2 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
- IEEE 1149.1-compatible boundary scan logic
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XC4000E output
- Unlimited re-programmability
- Program verification
- Internal node observability
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
- synchronous write option
- dual-port RAM option
networks
support
TM
memory: on-chip ultra-fast RAM with
R
0
0
0*
XC4000E and XC4000X Series Field
Programmable Gate Arrays
Product Specification
Low-Voltage Versions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000XL: High Performance Low-Voltage Versions of
Additional XC4000X Series Features
• High Performance — 3.3 V XC4000XL
• High Capacity — Over 180,000 Usable Gates
• 5 V tolerant I/Os on XC4000XL
• 0.35 m SRAM process for XC4000XL
• Additional Routing Over XC4000E
• Buffered Interconnect for Maximum Speed Blocks
• Improved VersaRing
• 12 mA Sink Current Per XC4000X Output
• Flexible New High-Speed Clock Network
• Optional Multiplexer or 2-input Function Generator on
• Four Additional Address Bits in Master Parallel
•
Introduction
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
members, as shown in
XC4000EX devices
- almost twice the routing capacity for high-density
Pinout Flexibility
- Eight additional Early Buffers for shorter clock delays
- Virtually unlimited number of clock signals
Device Outputs
Configuration Mode
0
designs
Table
TM
I/O Interconnect for Better Fixed
1.
6-5
6
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