XCV2000E-6FG860C Xilinx Inc, XCV2000E-6FG860C Datasheet - Page 78

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XCV2000E-6FG860C

Manufacturer Part Number
XCV2000E-6FG860C
Description
IC FPGA 1.8V C-TEMP 860-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet

Specifications of XCV2000E-6FG860C

Number Of Logic Elements/cells
43200
Number Of Labs/clbs
9600
Total Ram Bits
655360
Number Of I /o
660
Number Of Gates
2541952
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
860-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Virtex™-E 1.8 V Field Programmable Gate Arrays
Virtex-E Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Module 3 of 4
18
Notes:
1.
2.
3.
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, with
DLL. For data output with different standards,
adjust the delays with the values shown in
Output Switching Characteristics Standard
Adjustments, page
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
Table 3
DLL output jitter is already included in the timing calculation.
and
Table
Description
4.
10.
(1)
CC
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
IOB
T
Symbol
ICKOFDLL
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Device
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Speed Grade
Production Product Specification
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
-8
DS022-3 (v2.9.2) March 14, 2003
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
-7
(2, 3)
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
-6
Units
ns
ns
ns
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