XCV2600E-8FG1156C Xilinx Inc, XCV2600E-8FG1156C Datasheet

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XCV2600E-8FG1156C

Manufacturer Part Number
XCV2600E-8FG1156C
Description
IC FPGA 1.8V C-TEMP 1156-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet

Specifications of XCV2600E-8FG1156C

Number Of Logic Elements/cells
57132
Number Of Labs/clbs
12696
Total Ram Bits
753664
Number Of I /o
804
Number Of Gates
3263755
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1156-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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DS022-1 (v2.2) November 9, 2001
Features
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
Fast, High-Density 1.8 V FPGA Family
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Highly Flexible SelectI/O+™ Technology
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Differential Signalling Support
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Proprietary High-Performance SelectLink™
Technology
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Sophisticated SelectRAM+™ Memory Hierarchy
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* ZBT is a trademark of Integrated Device Technology, Inc.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Densities from 58 k to 4 M system gates
130 MHz internal performance (four LUT levels)
Designed for low-power operation
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
Supports 20 high-performance interface standards
Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
Differential I/O signals can be input, output, or I/O
Compatible with standard differential devices
LVPECL and LVDS clock inputs for 300+ MHz
clocks
Double Data Rate (DDR) to Virtex-E link
Web-based HDL generation methodology
1 Mb of internal configurable distributed RAM
Up to 832 Kb of synchronous internal block RAM
True Dual-Port™ BlockRAM capability
Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
Designed for high-performance Interfaces to
External Memories
200 MHz ZBT* SRAMs
200 Mb/s DDR SDRAMs
Supported by free Synthesizable reference design
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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www.xilinx.com
1-800-255-7778
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Virtex™-E 1.8 V
Field Programmable Gate Arrays
Preliminary Product Specification
High-Performance Built-In Clock Management Circuitry
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Flexible Architecture Balances Speed and Density
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Supported by Xilinx Foundation™ and Alliance Series™
Development Systems
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SRAM-Based In-System Configuration
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Advanced Packaging Options
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0.18
100% Factory Tested
Eight fully digital Delay-Locked Loops (DLLs)
Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
Clock Multiply and Divide
Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input function
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensor diode
Further compile time reduction of 50%
Internet Team Design (ITD) tool ideal for
million-plus gate density designs
Wide selection of PC and workstation platforms
Unlimited re-programmability
0.8 mm Chip-scale
1.0 mm BGA
1.27 mm BGA
HQ/PQ
m
m 6-Layer Metal Process
Module 1 of 4
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XCV2600E-8FG1156C Summary of contents

Page 1

R DS022-1 (v2.2) November 9, 2001 Features • Fast, High-Density 1.8 V FPGA Family - Densities from system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant ...

Page 2

... XCV1000E 1,569,178 331,776 XCV1600E 2,188,742 419,904 XCV2000E 2,541,952 518,400 XCV2600E 3,263,755 685,584 XCV3200E 4,074,387 876,096 Virtex-E Compared to Virtex Devices The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source ...

Page 3

R resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Con- figuration data can be ...

Page 4

... Min values added to Virtex-E Electrical Characteristics tables. 9/20/00 1.7 • XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics tables (Module 3). • Corrected user I/O count for XCV100E device in Table 1 (Module 1). • Changed several pins to “No Connect in the XCV100E“ and removed duplicate V pins in Table ~ (Module 4). • ...

Page 5

... Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices. • Revised Table 62 to include pinout information for the XCV400E and XCV600E devices in the BG560 package. • Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices. • Updated numerous values in 4/2/01 2.0 • ...

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