XC5VSX35T-1FFG665CES Xilinx Inc, XC5VSX35T-1FFG665CES Datasheet - Page 101
![IC FPGA VIRTEX-5 ES 35K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX35T-1FFG665CES
Manufacturer Part Number
XC5VSX35T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-1FFG665CES
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Total Ram Bits
3096576
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VSX35T-1FFG665CES
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
PLL Clock Input Signals
PLLs in the bottom half of the Virtex-5 device are driven by the global clock pins in bank4
and can be paired as listed in
Table 3-7: PLLs in the Bottom Half Pairing
Other important notes on these pairings:
•
•
•
The PLL clock source can come from several sources including:
•
•
•
•
The pin description names do not contain other possible multipurpose functions such
as _CC, _VRN, _VRP or _VREF.
Only the P-side pins are shown. For differential clock connections use the equivalent
N-side pin. Inside the FPGA, only the P-side of the differential pin pair can connect to
the CMT.
For a mapping to the actual pin numbers consult the Virtex-5 Family Packaging
Specifications.
IBUFG - Global clock input buffer, the PLL will compensate the delay of this path.
BUFGCTRL - Internal global clock buffer, the PLL will not compensate the delay of
this path.
IBUF - Not recommended since the PLL can not compensate for the delay of the
general route. An IBUF clock input must route to a BUFG before routing to a PLL.
DCMOUT - Any DCM output to PLL will compensate the delay of this path.
IO_L9P_GC_4
IO_L8P_GC_4
IO_L7P_GC_4
IO_L6P_GC_4
IO_L5P_GC_4
CLKIN1
www.xilinx.com
IO_L4P_GC_4
IO_L3P_GC_4
IO_L2P_GC_4
IO_L1P_GC_4
IO_L0P_GC_4
Table
CLKIN2
3-6.
General Usage Description
101
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