XC5VSX35T-1FFG665CES Xilinx Inc, XC5VSX35T-1FFG665CES Datasheet - Page 22
![IC FPGA VIRTEX-5 ES 35K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX35T-1FFG665CES
Manufacturer Part Number
XC5VSX35T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-1FFG665CES
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Total Ram Bits
3096576
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VSX35T-1FFG665CES
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Preface: About This Guide
Additional Support Resources
Typographical Conventions
22
•
•
•
•
To find additional documentation, see the Xilinx website at:
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
This document uses the following typographical conventions. An example illustrates each
convention.
Italic font
Virtex-5 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
Virtex-5 FPGA System Monitor User Guide
The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.
Virtex-5 FPGA Packaging and Pinout Specification
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
Virtex-5 FPGA PCB Designer’s Guide
This guide provides information on PCB design for Virtex-5 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
http://www.xilinx.com/support/documentation/index.htm.
http://www.xilinx.com/support.
Convention
References to other documents
Emphasis in text
www.xilinx.com
Meaning or Use
See the Virtex-5 FPGA Configuration
Guide for more information.
The address (F) is asserted after
clock event 2.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Example
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