AT94K10AL-25AQC Atmel, AT94K10AL-25AQC Datasheet - Page 100
AT94K10AL-25AQC
Manufacturer Part Number
AT94K10AL-25AQC
Description
IC FPSLIC 10K GATE 25MHZ 100TQFP
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K10AL-25AQC
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
20K-32K
Fpga Sram
4kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
576
Fpga Gates
10K
Fpga Registers
846
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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AT94KAL Series FPSLIC
• Description of wake-up from Power-save mode when the timer is clocked asynchronously.
• During asynchronous operation, the synchronization of the interrupt flags for the
down, the user should be aware of the fact that this oscillator might take as long as one
second to stabilize. Therefore, the contents of all Timer2 registers must be considered lost
after a wake-up from power-down, due to the unstable clock signal. The user is advised to
wait for at least one second before using Timer/Counter2 after power-up or wake-up from
power-down.
When the interrupt condition is met, the wake-up process is started on the following cycle of
the timer clock, that is, the timer is always advanced by at least one before the processor can
read the counter value. The interrupt flags are updated three processor cycles after the
processor clock has started. During these cycles, the processor executes instructions, but
the interrupt condition is not readable, and the interrupt routine has not started yet.
asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting of
the interrupt flag. The output compare pin is changed on the timer clock and is not
synchronized to the processor clock.
1138I–FPSLI–1/08
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