AT94K05AL-25BQC Atmel, AT94K05AL-25BQC Datasheet - Page 55
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AT94K05AL-25BQC
Manufacturer Part Number
AT94K05AL-25BQC
Description
IC FPSLIC 5K GATE 25MHZ 144LQFP
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K05AL-25BQC
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
4K-16K
Fpga Sram
2kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
256
Fpga Gates
5K
Fpga Registers
436
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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4.14
1138I–FPSLI–1/08
FPGA I/O Selection by AVR
Sixteen select signals are sent to the FPGA for I/O addressing. These signals are decoded from
four I/O registry addresses (FISUA...D) and extended to sixteen with two bits from the FPGA I/O
Select Control Register (FISCR). In addition, the FPGAIORE and FPGAIOWE signals are quali-
fied versions of the IORE and IOWE signals. Each will only be active if one of the four base I/O
addresses are referenced. It is necessary for the FPGA design to implement any required regis-
ters for each select line; each qualified with either the FPGAIORE or FPGAIOWE strobe. Refer
to the FPGA/AVR Interface section for more details. Only the FISCR registers physically exist.
The FISUA...D I/O addresses for the purpose of FPGA I/O selection are NOT supported by AVR
Core I/O space registers; they are simply I/O addresses (available to 1 cycle IN/OUT instruc-
tions) which trigger appropriate enabling of the FPGA select lines and the FPGA IORE/IOWE
strobes (see
FPGA I/O Select Control Register – FISCR
• Bit 7 - FIADR: FPGA Interrupt Addressing Enable
When FIADR is set (one), the four dual-purpose I/O addresses, FISUA..D, are mapped to four
physical registers that provide memory space for FPGA interrupt masking and interrupt flag sta-
tus. When FIADR is cleared (zero), an I/O read or write to one of the four dual-purpose I/O
addresses, FISUA..D, will access its associated group of four FPGA I/O select lines. The XFIS1
and XFIS0 bits (see
set (one). A read will assign the FPGA I/O read enable to the AVR I/O read enable (FPGAIORE
←
IOWE). FPGA macros utilizing one or more FPGA I/O select lines must use the FPGA I/O
read/write enables, FPGAIORE or FPGAIOWE, to qualify each select line. The FIADR bit
will be cleared (zero) during AVR reset.
• Bits 6..2 - Res: Reserved Bits
These bits are reserved and always read as zero.
• Bits 1, 0 - XFIS1, 0: Extended FPGA I/O Select Bits 1, 0
XFIS[1:0] determines which one of the four FPGA I/O select lines will be set (one) within the
accessed group. An I/O read or write to one of the four dual-purpose I/O addresses, FISUA..D,
will access one of four groups.
Bit
$13 ($33)
Read/Write
Initial Value
IORE) and a write, the FPGA I/O write enable to the AVR I/O write enable (FPGAIOWE
Figure 3-1
7
FIADR
R/W
0
Table
on
6
-
R
0
4-4) further determine which one select line in the accessed group is
page
Table 4-4
21).
5
-
R
0
details the FPGA I/O selection scheme.
4
-
R
0
AT94KAL Series FPSLIC
3
-
R
0
2
-
R
0
1
XFIS1
R/W
0
0
XFIS0
R/W
0
FISCR
55
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