AT94K05AL-25AQU Atmel, AT94K05AL-25AQU Datasheet - Page 5

• Manufacturer Part Number: AT94K05AL-25AQU
• Description: IC FPSLIC 5K GATE 25MHZ 100-TQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25AQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.4
2.5
1138I–FPSLI–1/08
Automatic Component Generators
The Symmetrical Array
functions are required, they can be loaded into the logic cache without losing the data already
there or disrupting the operation of the rest of the chip; replacing or complementing the active
logic. The AT40K FPGA core can act as a reconfigurable resource within the FPSLIC
environment.
The AT40K is capable of implementing user-defined, automatically generated, macros; speed
and functionality are unaffected by the macro orientation or density of the target device. This
enables the fastest, most predictable and efficient FPGA design approach and minimizes design
risk by reusing already proven functions. The Automatic Component Generators work seam-
lessly with industry-standard schematic and synthesis tools to create fast, efficient designs.
The patented AT40K architecture employs a symmetrical grid of small yet powerful cells con-
nected to a flexible busing network. Independently controlled clocks and resets govern every
column of four cells. The FPSLIC device is surrounded on three sides by programmable I/Os.
Core usable gate counts range from 5,000 to 40,000 gates and 436 to 2,864 registers. Pin loca-
tions are consistent throughout the FPSLIC family for easy design migration in the same
package footprint.
The Atmel AT40K FPGA core architecture was developed to provide the highest levels of perfor-
mance, functional density and design flexibility. The cells in the FPGA core array are small,
efficient and can implement any pair of Boolean functions of (the same) three inputs or any sin-
gle Boolean function of four inputs. The cell’s small size leads to arrays with large numbers of
cells. A simple, high-speed busing network provides fast, efficient communication over medium
and long distances.
At the heart of the Atmel FPSLIC architecture is a symmetrical array of identical cells. The array
is continuous from one edge to the other, except for bus repeaters spaced every four cells, see
Figure
ble by adjacent buses. The RAM can be configured as either a single-ported or dual-ported
RAM, with either synchronous or asynchronous operation.
2-1. At the intersection of each repeater row and column is a 32 x 4 RAM block accessi-
AT94KAL Series FPSLIC
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