MB86R01PB-GSE1 Fujitsu Semiconductor America Inc, MB86R01PB-GSE1 Datasheet - Page 9

• Manufacturer Part Number: MB86R01PB-GSE1
• Description: IC SOC GRAPHIC CONTRLR 484BGA
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of MB86R01PB-GSE1

• Applications: Graphics Controller
• Core Processor: ARM9
• Program Memory Type: External Program Memory
• Controller Series: Jade
• Ram Size: 64K x 8
• Interface: ADC, ATA, CAN, EBI/EMI, I²C, I²S, Media LB, PWM, SD Card, UART/USART, USB
• Number Of I /o: 24
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1110

MB86R01 DATA SHEET
FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
AHB1 bus
Following resources are connected.
AHB2 bus
APB_TOP_0
This block bridges between APBBRG0 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
APB_TOP_1
This block bridges between APBBRG1 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
APB_TOP_2
This block bridges between APBBRG2 bus and AHB1 bus, and following low-speed peripheral resources
are connected.
• CPU core: Bus masters of instruction (I)/data (D)
• GDC: GDC register part
• AHB2AXI: AXI port for main memory access
• CCPB: Encrypted ROM decoding block
• External BUS I/F: External bus interface (connected through CCPB)
• SRAM: General purpose internal SRAM 32KB × 2
• DMAC: General purpose DMA × 8ch
• Boot ROM: Built-in boot ROM
• I2S_0/1/2: Serial audio controller × 3ch
• USB 2.0 Function DMAC: USB function DMAC
• USB2.0 Host: It operates as USB2.0 EHCI, USB1.1 OHCI bus masters
• IDE66/IDE66DMAC: Register part of IDE host controller and built-in DMAC
• MLB: MediaLB controller
• AHB2
• APBBRG0/1/2: AHB-APB bridge circuit × 3ch
• CCPB: Encrypted ROM decoding block
• USB 2.0 Function: USB 2.0 function controller's register part
• USB 2.0 Host: USB 2.0 host controller's register part
• SDMC: SD memory controller
• DDR2 controller: DDR2 controller's register part
• Interrupt controller (IRC) × 2ch
• External interrupt controller (EXTIRC)
• Clock reset generator (CRG)
• UART (ch0 and ch1) × 2ch
• Remap boot controller (RBC)
• 32 bit general-purpose timer (32 bit timer) × 2ch
• I
• CAN controller × 2ch
• UART (ch2 and ch3) × 2ch
• A/D converter (ADC) × 2ch
• PWM controller (PWM)
• SPI controller (SPI)
• CCNT
• UART (ch4 and ch5) × 2ch
It operates as bus master at data transfer
It operates as bus master at data transfer
The DMAC part operates as bus master at data transfer
2
C controller × 2ch
3