CY7C64713-56PVXC Cypress Semiconductor Corp, CY7C64713-56PVXC Datasheet - Page 47

• Manufacturer Part Number: CY7C64713-56PVXC
• Description: IC MCU USB EZ FX1 16KB 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-56PVXC

• Program Memory Type: ROMless
• Package / Case: 56-SSOP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3674
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Sequence Diagram of a Single and Burst Asynchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 35
in an asynchronous mode. This diagram shows a single write
followed by a burst write of 3 bytes and committing the
4-byte-short packet using PKTEND.
■
■
■
■
Document #: 38-08039 Rev. *F
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of t
(SLCS may be tied low in some applications).
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
t
or before SLWR is asserted.
At t = 2, data must be present on the bus t
deasserting edge of SLWR.
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
WRpwh
FIFOADR
PKTEND
FLAGS
SLWR
DATA
SLCS
. If the SLCS is used, it must be in asserted with SLWR
shows the timing relationship of the SLAVE FIFO write
SFA
t=0
WRpwl
t
SFA
. If SLCS is used, it must also be asserted
t =1
and minimum de-active pulse width of
t
WRpwl
t=2
Figure 35. Slave FIFO Asynchronous Write Sequence and Timing Diagram
t
SFD
t=3
t
N
t
FDH
WRpwh
t
FAH
t
XFLG
SFD
T=0
before the
t
SFA
T=1
t
WRpwl
T=2
t
SFD
T=3
t
N+1
FDH
t
WRpwh
T=4
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incre-
mented.
In
SLWR is deasserted, the short 4-byte packet is committed to the
host using the PKTEND. The external device must be designed
to not assert SLWR and the PKTEND signal at the same time. It
must be designed to assert the PKTEND after SLWR is
deasserted and has met the minimum deasserted pulse width.
The FIFOADDR lines are to be held constant during the
PKTEND assertion.
t
WRpwl
The FIFO flag is also updated after t
edge of SLWR.
T=5
Figure
t
SFD
T=6
t
N+2
FDH
t
WRpwh
35, after the four bytes are written to the FIFO and
T=7
t
WRpwl
T=8
t
SFD
T=9
t
t
N+3
WRpwh
FDH
XFLG
t
PEpwl
from the deasserting
CY7C64713
t
XFLG
t
PEpwh
t
FAH
Page 47 of 55
[+] Feedback