CY8CTMG200-32LQXI Cypress Semiconductor Corp, CY8CTMG200-32LQXI Datasheet - Page 73
CY8CTMG200-32LQXI
Manufacturer Part Number
CY8CTMG200-32LQXI
Description
IC MCU 32K FLASH 32UQFN
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTMG200-32LQXI
Program Memory Type
FLASH (32 kB)
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Applications
Touchscreen Controller
Core Processor
M8C
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Mounting Style
SMD/SMT
Program Memory Size
32 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2954
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This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep
and Watchdog registers, refer to the
isters in address order, refer to the
10.1
Device components that are involved in Sleep and Watchdog operation are the selected 32 kHz clock, the wakeup timer, the
Sleep bit in the CPU_SCR0 register, the sleep circuit (to sequence going into and coming out of sleep), the bandgap refresh
circuit (to periodically refresh the reference voltage during sleep), and the watchdog timer.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
10. Sleep and Watchdog
Architectural Description
32 kHz CLK
CPU_SCR0
OSC_SCR0
Sleep Timer
(SLP_CFG, SLP_CFG2,
Configuration Registers)
Register Decode Logic
SLP_CFG3, Internal
Register Reference chapter on page
IMO
CLK
Summary Table of the Core Registers on page
Figure 10-1. Sleep Controller Architecture
Wakeup Timer
CPU Hold
Off
187.
Sleep Control Logic
Control Inputs
24. For a quick reference of all PSoC reg-
Outputs
[+] Feedback
73
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