CY7C68014A-128AXC Cypress Semiconductor Corp, CY7C68014A-128AXC Datasheet - Page 50

IC MCU USB PERIPH HI SPD 128LQFP

CY7C68014A-128AXC

Manufacturer Part Number
CY7C68014A-128AXC
Description
IC MCU USB PERIPH HI SPD 128LQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r

Specifications of CY7C68014A-128AXC

Program Memory Type
ROMless
Package / Case
128-LQFP
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
40
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Processor Series
CY7C68xx
Core
8051
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C/USART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
40
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3684
Minimum Operating Temperature
0 C
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
40
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Package
128TQFP
Device Core
8051
Family Name
FX2LP
Maximum Speed
48 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1671

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C68014A-128AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
9.16 Slave FIFO Asynchronous Address
Table 9-1. Slave FIFO Asynchronous Address Parameters
9.17 Sequence Diagram
9.17.1 Single and Burst Synchronous Read Example
Document #: 38-08032 Rev. *T
t
t
SFA
FAH
FIFO POINTER
FLAGS
FIFO DATA BUS
FIFOADR
SLRD
SLCS
DATA
IFCLK
SLOE
Parameter
Not Driven
t=0
IFCLK
N
FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time
RD/WR/PKTEND to FIFOADR[1:0] hold time
Figure 9-18. Slave FIFO Synchronous Read Sequence and Timing Diagram
SLRD/SLWR/PKTEND
SLCS/FIFOADR [1:0]
t=1
SLOE
t
SFA
Figure 9-17. Slave FIFO Asynchronous Address Timing Diagram
Figure 9-19. Slave FIFO Synchronous Sequence of Events Diagram
t
OEon
Data Driven: N
t=2
Driven: N
t
SRD
IFCLK
N
t
IFCLK
t
XFD
t=3
t
SLRD
RDH
t
XFLG
Description
t
OEoff
N+1
t=4
N+1
t
IFCLK
N+1
FAH
SLOE
SLRD
Not Driven
t
SFA
IFCLK
[23]
t
N+1
T=0
SFA
t
OEon
SLOE
T=2
>= t
T=1
N+1
IFCLK
N+1
SRD
N+1
SLRD
t
XFD
t
Min
FAH
N+2
10
10
N+2
IFCLK
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
N+2
N+3
N+3
IFCLK
t
XFD
N+4
N+4
Max
IFCLK
[20]
N+3
SLRD
[20]
t
>= t
XFD
RDH
N+4
N+4
IFCLK
t
N+4
OEoff
SLOE
T=3
T=4
t
FAH
Unit
ns
ns
Page 50 of 67
Not Driven
IFCLK
N+4
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