ATAM862P-TNSY3D Atmel, ATAM862P-TNSY3D Datasheet - Page 23
![IC MCU FLASH 4K TX 315MHZ 24SSOP](/photos/6/76/67636/453-24-ssop_sml.jpg)
ATAM862P-TNSY3D
Manufacturer Part Number
ATAM862P-TNSY3D
Description
IC MCU FLASH 4K TX 315MHZ 24SSOP
Manufacturer
Atmel
Datasheet
1.ATAM862P-TNQY3D.pdf
(110 pages)
Specifications of ATAM862P-TNSY3D
Applications
UHF ASK/FSK
Core Processor
MARC4
Program Memory Type
FLASH (4 kB)
Controller Series
MARC4 4-Bit
Ram Size
256 x 4
Interface
SSI
Number Of I /o
11
Voltage - Supply
1.8 V ~ 4 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Processor Series
ATAM862x
Core
MARC4
Data Bus Width
4 bit
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
17. Master Reset
17.1
4554F–4BMCU–07/07
Power-on Reset and Brown-out Detection
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated
independent of the current program state. It can be triggered by either initial supply power-up, a
short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an exter-
nal input clock supervisor stage (see
interrupt enable flag, the interrupt pending register and the interrupt active register. During the
power-on reset phase, the I/O bus control signals are set to reset mode, thereby, initializing all
on-chip peripherals. All bi-directional ports are set to input mode
Attention: During any reset phase, the BP20/NTE input is driven towards V
internal strong pull-up transistor. This pin must not be pulled down to V
external circuitry representing a resistor of less than 150 kΩ.
Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h.
This activates the initialization routine $RESET which in turn has to initialize all necessary RAM
variables, stack pointers and peripheral configuration registers (see
Figure 17-1. Reset Configuration
The microcontroller block has a fully integrated power-on reset and brown-out detection circuitry.
For reset generation no external components are needed.
These circuits ensure that the core is held in the reset state until the minimum operating supply
voltage has been reached. A reset condition will also be generated should the supply voltage
drop momentarily below the minimum operating level except when a power-down mode is acti-
vated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-down
mode the brown-out detection is disabled.
Two values for the brown-out voltage threshold are programmable via the BOT bit in the
SC register.
NRST
V
DD
Pull-up
Figure
17-1). A master reset activation will reset the
CL
res
CL=SYSCL/4
supervisor
Power-on
Brown-out
Ext. clock
detection
Watch-
Reset
timer
reset
dog
res
Table 21-1 on page
SS
ATAM862-3
Internal
V
V
V
V
CWD
ExIn
reset
DD
SS
DD
SS
during reset by any
DD
by an additional
34).
23