AT43USB320A-AC Atmel, AT43USB320A-AC Datasheet - Page 30

• Manufacturer Part Number: AT43USB320A-AC
• Description: IC USB MCU EMBED HUB AVR 100LQFP
• Manufacturer: Atmel
• Series: AVR®r

Specifications of AT43USB320A-AC

• Applications: USB Hub/Microcontroller
• Core Processor: AVR
• Controller Series: AT43USB
• Ram Size: 512 x 8
• Interface: SPI Serial, USB, UART
• Number Of I /o: 32
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Type: -

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AT43USB320A
MCU Control Register – MCUCR
• Bit 7, 6 – Res: Reserved Bits
• Bit 5 – SE: Sleep Enable
The SE bit must be set (1) to make the MCU enter the sleep mode when the SLEEP instruc-
tion is executed. To avoid the MCU entering the sleep mode, unless it is the programmer's
purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the
SLEEP instruction.
• Bit 4 – SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode
is selected as Sleep Mode. When SM is set (1), Power Down mode is selected as sleep mode.
The AT43USB320A does not support the Idle Mode and SM should always be set to one when
entering the Sleep Mode.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask in the GIMSK is set. The level and edges on the external INT1 pin
that activate the interrupt are defined in the following table:
Table 8. INT1 Sense Control
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 bit 1 and bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask in the GIMSK is set. The level and edges on the external INT1 pin
that activate the interrupt are defined in the following table:
Table 9. INT1 Sense Control
Initial Value
Read/Write
$35 ($55)
ISC11
ISC01
Bit
0
0
1
1
0
0
1
1
7
–
R
0
ISC10
ISC00
0
1
0
1
0
1
0
1
R
6
–
0
Description
The low level of INT1 generates an interrupt request.
Reserved.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
Description
The low level of INT1 generates an interrupt request.
Reserved.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
R/W
SE
5
0
R/W
SM
4
0
ISC11
R/W
3
0
ISC10
R/W
2
0
ISC01
R/W
1
0
ISC00
R/W
0
0
1443E–USB–4/04
MCUCR