CY7C63413C-PXC Cypress Semiconductor Corp, CY7C63413C-PXC Datasheet - Page 19

• Manufacturer Part Number: CY7C63413C-PXC
• Description: IC MCU 8K USB LS PERIPH 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1853

Document #: 38-08027 Rev. *B
The “Single Step” (bit 1) is provided to support a hardware
debugger. When single step is set, the processor will execute
one instruction and halt (clear the run bit). This bit must be
cleared for normal operation.
The “Interrupt Mask” (bit 2) shows whether interrupts are
enabled or disabled. The firmware has no direct control over
this bit as writing a zero or one to this bit position will have no
effect on interrupts. Instructions DI, EI, and RETI manipulate
the internal hardware that controls the state of the interrupt
mask bit in the Processor Status and Control Register.
Writing a “1” to “Suspend, Wait for Interrupts” (bit 3) will halt
the processor and cause the microcontroller to enter the
“suspend”
consumption. A pending interrupt or bus activity will cause the
device to come out of suspend. After coming out of suspend,
the device will resume firmware execution at the instruction
following the IOWR which put the part into suspend. An IOWR
that attempts to put the part into suspend will be ignored if
either bus activity or an interrupt is pending.
The “Power-on Reset” (bit 4) is only set to “1” during a power
on reset. The firmware can check bits 4 and 6 in the reset
handler to determine whether a reset was caused by a Power
On condition or a Watch Dog Timeout. PORS is used to
determine suspend start-up timer value of 128 µs or 96 ms.
The “USB Bus Reset” (bit 5) will occur when a USB bus reset
is received. The USB Bus Reset is a singled-ended zero (SE0)
that lasts more than 8 microseconds. An SE0 is defined as the
condition in which both the D+ line and the D– line are LOW
at the same time. When the SIE detects this condition, the
USB Bus Reset bit is set in the Processor Status and Control
register and an USB Bus Reset interrupt is generated. Please
note this is an interrupt to the microcontroller and does not
actually reset the processor.
The “Watch Dog Reset” (bit 6) is set during a reset initiated by
the Watch Dog Timer. This indicates the Watch Dog Timer
went for more than 8 ms between watch dog clears.
The “IRQ Pending” (bit 7) indicates one or more of the inter-
rupts has been recognized as active. The interrupt
acknowledge sequence should clear this bit until the next
interrupt is detected.
Table 25.Global Interrupt Enable Register
Table 26.USB End Point Interrupt Enable Register
Reserved
Reserved
7
7
Addr: 0x20
Addr: 0x21
mode
Reserved
Reserved
that
6
6
significantly
Reserved
Interrupt
Enable
GPIO
R/W
5
5
USB End Point Interrupt Enable Register
reduces
Global Interrupt Enable Register
Reserved
Interrupt
Enable
DAC
R/W
4
4
power
During Power-on Reset, the Processor Status and Control
Register is set to 00010001, which indicates a Power-on Reset
(bit 4 set) has occurred and no interrupts are pending (bit 7
clear) yet.
During a Watch Dog Reset, the Processor Status and Control
Register is set to 01000001, which indicates a Watch Dog
Reset (bit 6 set) has occurred and no interrupts are pending
(bit 7 clear) yet.
Interrupts
All interrupts are maskable by the Global Interrupt Enable
Register and the USB End Point Interrupt Enable Register.
Writing a “1” to a bit position enables the interrupt associated
with that bit position. During a reset, the contents the Global
Interrupt Enable Register and USB End Point Interrupt Enable
Register are cleared, effectively disabling all interrupts.
Pending interrupt requests are recognized during the last clock
cycle of the current instruction. When servicing an interrupt,
the hardware will first disable all interrupts by clearing the
Interrupt Enable bit in the Processor Status and Control
Register. Next, the interrupt latch of the current interrupt is
cleared. This is followed by a CALL instruction to the ROM
address associated with the interrupt being serviced (i.e., the
Interrupt Vector). The instruction in the interrupt table is
typically a JMP instruction to the address of the Interrupt
Service Routine (ISR). The user can re-enable interrupts in the
interrupt service routine by executing an EI instruction. Inter-
rupts can be nested to a level limited only by the available
stack space.
The Program Counter value as well as the Carry and Zero
flags (CF, ZF) are automatically stored onto the Program Stack
by the CALL instruction as part of the interrupt acknowledge
process. The user firmware is responsible for insuring that the
processor state is preserved and restored during an interrupt.
The PUSH A instruction should be used as the first command
in the ISR to save the accumulator value and the POP A
instruction should be used just before the RETI instruction to
restore the accumulator value. The program counter CF and
ZF are restored and interrupts are enabled when the RETI
instruction is executed.
Reserved
Reserved
3
3
1.024-ms
Interrupt
Interrupt
Enable
Enable
EPA2
R/W
R/W
2
2
128-µsec
Interrupt
Interrupt
Enable
Enable
EPA1
R/W
R/W
1
1
CY7C63413C
CY7C63513C
CY7C63613C
USB Bus RST
Page 19 of 32
Interrupt
Interrupt
Enable
Enable
EPA0
R/W
R/W
0
0
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