CY7C67300-100AXE Cypress Semiconductor Corp, CY7C67300-100AXE Datasheet - Page 13

• Manufacturer Part Number: CY7C67300-100AXE
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXE

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Minimum Hardware Requirements for Standalone Mode – Peripheral Only
Power Savings and Reset Description
This sections describes the different modes for resetting the chip
and ways to save power.
Power Saving Mode Description
EZ-Host has one main power saving mode, Sleep. For detailed
information about Sleep mode, see the
follows.
Sleep mode is used for USB applications to support USB
suspend and non USB applications as the main chip power down
mode.
In addition, EZ-Host is capable of slowing down the CPU clock
speed through the CPU Speed register [0xC008] without
affecting other peripheral timing. Reducing the CPU clock speed
from 48 MHz to 24 MHz reduces the overall current draw by
around 8 mA while reducing it from 48 MHz to 3 MHz reduces
the overall current draw by approximately 15 mA.
Document #: 38-08015 Rev. *J
*Bootloading begins after POR + 3ms BIOS bootup
*GPIO[31:30]
Up to 2k x8
>2k x8 to 64k x8
GND
Standard-B
or Mini-B
A0
A1
A2
Figure 9. Minimum Standalone Hardware Configuration – Peripheral Only
Up to 64k x8
EEPROM
SCL SDA
SDA SCL
31
SHIELD
VBus
D+
D-
GND
30
VCC
WP
SCL
SDA
VCC
Vcc
Sleep
10k
Bootstrap Options
Vcc
VReg
10k
Bootloading Firmware
section that
GPIO[30]
GPIO[31]
VCC, AVCC,
BoostVCC
DPlus
DMinus
SCL*
SDA*
Reserved
GND, AGND,
BoostGND
Sleep
Sleep mode is the main chip power down mode and is also used
for USB suspend. Sleep mode is entered by setting the Sleep
Enable (bit 1) of the Power control register [0xC00A]. During
Sleep mode (USB Suspend) the following events and states are
true:
■
■
■
■
■
■
■
■
CY7C67300
GPIO pins maintain their configuration during sleep (in
suspend)
External Memory address pins are driven low
XTALOUT is turned off
Internal PLL is turned off
Ensure that firmware disables the charge pump (OTG Control
register [0xC098]) thereby causing OTGVBUS to drop below
0.2V. Otherwise OTGVBUS only drops to V
diode drops).
Booster circuit is turned off
USB transceivers is turned off
CPU goes into suspend mode until a programmable wakeup
event
EZ-Host
Code / Data
Int. 16k x8
nRESET
XOUT
Pin 38
XIN
* Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
VCC
12MHz
47Kohm
Reset
Logic
22pf
22pf
CY7C67300
CC
– (2 schottky
Page 13 of 99
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