EZ80L92AZ020SG Zilog, EZ80L92AZ020SG Datasheet - Page 41
EZ80L92AZ020SG
Manufacturer Part Number
EZ80L92AZ020SG
Description
IC WEBSERVER 20MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3876
EZ80L92AZ020SG
EZ80L92AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ020SG
Manufacturer:
SYNERGY
Quantity:
5 000
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PS013014-0107
Clock Peripheral Power-Down Registers
The eZ80 CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
To minimize current in HALT mode, the system clock must be disabled for all unused on-
chip peripherals through the Clock Peripheral Power-Down Registers.
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be disabled to unused on-chip peripherals. On RESET, all peripherals are enabled. The
clock to unused peripherals can be disabled by setting the appropriate bit in the Clock
Peripheral Power-Down Registers to 1. When powered down, the peripherals are com-
pletely disabled. To re-enable, the bit in the Clock Peripheral Power-Down Registers must
be cleared to 0.
Many peripherals feature separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the standard peripheral control registers are not accessible for Read or Write access.
See
Non-maskable interrupt (NMI).
Maskable interrupt.
RESET through the external RESET pin driven Low.
Watchdog Timer time-out (if configured to generate either an NMI or RESET upon
time-out).
RESET through execution of a Debug RESET command.
Table 4
and
Table
5.
Product Specification
Low-Power Modes
35
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