EZ80L92AZ020SG Zilog, EZ80L92AZ020SG Datasheet - Page 71
EZ80L92AZ020SG
Manufacturer Part Number
EZ80L92AZ020SG
Description
IC WEBSERVER 20MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ020SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3876
EZ80L92AZ020SG
EZ80L92AZ020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ020SG
Manufacturer:
SYNERGY
Quantity:
5 000
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Table 20. Motorola Bus Mode Read States (Continued)
Table 21. Motorola Bus Mode Write States
PS013014-0107
STATE S6
STATE S7
STATE S0
STATE S1
STATE S2
STATE S3
STATE S4
STATE S5
STATE S6
STATE S7
During state S6, data from the external peripheral device is driven onto the data bus.
On the rising edge of the clock entering state S7, the CPU latches data from the addressed
peripheral device and deasserts AS and DS. The peripheral device deasserts DTACK at
this time.
The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves R/
W Low).
Entering S1, the CPU drives a valid address on the address bus.
On the rising edge of S2, the CPU asserts AS and drives R/W Low.
During S3, the data bus is driven out of the high-impedance state as the data to be written is
placed on the bus.
At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal
DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period
prior to the rising clock edge at the end of S4, the CPU inserts WAIT (T
DTACK is asserted. Each WAIT state is a full bus mode cycle.
During S5, no bus signals are altered.
During S6, no bus signals are altered.
Upon entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the
CPU drives R/W High. The peripheral device deasserts DTACK at this time.
The eight states for a Write operation in Motorola Bus Mode are described in
Chip Selects and Wait States
Product Specification
WAIT
) states until
eZ80L92 MCU
Table
21.
65
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