MPC8349VVALFB Freescale Semiconductor, MPC8349VVALFB Datasheet - Page 46
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MPC8349VVALFB
Manufacturer Part Number
MPC8349VVALFB
Description
IC MPU POWERQUICC II 672-TBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheet
1.MPC8349VVALFB.pdf
(87 pages)
Specifications of MPC8349VVALFB
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
667MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
672-TBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
667MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.3V
Operating Supply Voltage (max)
1.36V
Operating Supply Voltage (min)
1.24V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
TBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
667MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
TBGA
No. Of Pins
672
Rohs Compliant
Yes
For Use With
MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8349VVALFB
Manufacturer:
AD
Quantity:
8 557
Company:
Part Number:
MPC8349VVALFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
I
Figure 31
Figure 32
46
2
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Notes:
1. The symbols for timing specifications follow the pattern of t
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
5.)The device does not follow the “I
C
and t
respect to the time data input signals (D) reach the valid state (V) relative to the t
state or setup time. Also, t
goes invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
the undefined region of the falling edge of SCL.
B
SDA
SCL
= capacitance of one bus line in pF.
(first two letters of functional block)(reference)(state)(signal)(state)
provides the AC test load for the I
shows the AC timing diagram for the I
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
S
I2DVKH
t
I2CF
t
I2CL
t
I2SXKL
must be met only if the device does not stretch the LOW period (t
Output
I2SXKL
Parameter
Table 43. I
I2C
2
symbolizes I
C-BUS Specifications” version 2.1 regarding the t
clock reference (K) going to the low (L) state or hold time. Also, t
5
Figure 32. I
t
I2DXKL
2
C AC Electrical Specifications (continued)
Figure 31. I
2
t
C timing (I2) for the time that the data with respect to the start condition (S)
Z
I2DVKH
0
= 50 Ω
t
2
I2CH
2
C.
C Bus AC Timing Diagram
2
t
I2SXKL
2
C bus.
C AC Test Load
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
Sr
t
I2SVKH
Symbol
R
t
t
t
I2KHDX
I2KHKL
I2PVKH
t
V
L
V
I2CF
NH
NL
= 50 Ω
I2C
1
clock reference (K) going to the high (H)
I2CF
I2DVKH
0.1 × OV
0.2 × OV
IH
t
AC parameter.
I2PVKH
OV
I2CL
(min) of the SCL signal) to bridge
Min
0.6
1.3
DD
__
symbolizes I
) of the SCL signal.
t
I2CR
/2
DD
DD
Freescale Semiconductor
I2PVKH
P
2
Max
t
300
I2CF
C timing (I2) with
—
—
—
—
symbolizes I
S
for inputs
I2C
Unit
μs
μs
ns
clock
V
V
2
C