MPC8541ECVTALF Freescale Semiconductor, MPC8541ECVTALF Datasheet - Page 51

• Manufacturer Part Number: MPC8541ECVTALF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8541ECVTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

All values refer to V
12.2
Table 40
Freescale Semiconductor
SCL clock frequency
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
Data setup time
Data hold time:
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. MPC8541E provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
5. Guaranteed by design.
for inputs and t
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
high (H) state or setup time. Also, t
condition (S) went invalid (X) relative to the t
symbolizes I
to the t
with the appropriate letter: R (rise) or F (fall).
undefined region of the falling edge of SCL.
B
= capacitance of one bus line in pF.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
I2C
provides the AC timing parameters for the I
I
2
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used
C AC Electrical Specifications
2
C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative
IH
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
(min) and V
has only to be met if the device does not stretch the LOW period (t
Parameter
IL
(max) levels (see
I2SXKL
Table 40. I
CBUS compatible masters
symbolizes I
Table
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
2
C AC Electrical Specifications
39).
I
2
C bus devices
2
C timing (I2) for the time that the data with respect to the start
2
C interface of the MPC8541E.
for outputs. For example, t
Symbol
t
t
t
t
t
I2SVKH
I2DVKH
t
(first two letters of functional block)(signal)(state) (reference)(state)
I2SXKL
I2PVKH
I2KHDX
t
I2DXKL
t
t
t
I2CH
I2CL
V
V
f
I2CR
I2CF
I2C
NH
NL
6
6
6
6
6
1
20 + 0.1 C
20 + 0.1 C
0.1 × OV
0.2 × OV
IHmin
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
0
—
0
I2C
I2CL
2
of the SCL signal) to bridge the
clock reference (K) going to the
DD
DD
) of the SCL signal.
b
b
I2DVKH
4
4
symbolizes I
0.9
Max
400
300
300
—
—
—
—
—
—
—
—
—
—
3
I2PVKH
2
C timing
Unit
kHz
ns
μs
μs
μs
μs
μs
ns
ns
μs
μs
V
V
I2C
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