MPC8541ECVTALF Freescale Semiconductor, MPC8541ECVTALF Datasheet - Page 79

• Manufacturer Part Number: MPC8541ECVTALF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8541ECVTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

17.6
The MPC8541E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up
devices.
17.7
The MPC8541E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type
pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion give
unpredictable results.
TSEC1_TXD[3:0] must not be pulled low during reset. Some PHY chips have internal pulldowns that
could cause this to happen. If such PHY chips are used, then a pullup must be placed on these signals strong
enough to restore these signals to a logical 1 during reset.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
17.8
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture. The
device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not
interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using
only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply
tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common
on-chip processor (COP) function.
Freescale Semiconductor
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Pull-Up Resistor Requirements
Configuration Pin Multiplexing
JTAG Configuration Signals
Figure
52. Care must be taken to ensure that these pins are maintained at a valid deasserted
System Design Information
79