MPC8540PX667LB Freescale Semiconductor, MPC8540PX667LB Datasheet - Page 14

• Manufacturer Part Number: MPC8540PX667LB
• Description: IC MPU 32BIT 667MHZ 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8540PX667LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548MPC8540ADS-BGA - BOARD APPLICATION DEV 8540CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

MPC8540 Architecture Overview
3.9 10/100 Fast Ethernet Controller
The MPC8540 provides a 10/100 fast Ethernet controller operating at 10 to 100 Mbps as a device debug and
maintenance port. The gigabit three-speed Ethernet controllers (TSECs) are separate from this 10/100 fast Ethernet
controller and are defined and described in Chapter 13, “Three-Speed Ethernet Controllers,” in the MPC8540
Integrated Host Processor Reference Manual.
The 10/100 Ethernet standard supports the IEEE 802.3 Ethernet frame format, backward compatibility for installed
media, and the use of full- or half-duplex CSMA/CD. The Ethernet protocol implements the bottom two layers of
the open systems interconnection (OSI) 7-layer model, that is, the data-link and physical sublayers.
3.10 Local Bus Controller (LBC)
The MPC8540 local bus controller (LBC) port allows connections with a wide variety of external memories, DSPs,
and ASICs. Three separate state machines share the same external pins and can be programmed separately to access
different types of devices. The general-purpose chip select machine (GPCM) controls accesses to asynchronous
devices using a simple handshake protocol. The user programmable machine (UPM) can be programmed to
interface to synchronous devices or custom ASIC interfaces. The SDRAM controller provides access to standard
SDRAM. Each chip select can be configured so that the associated chip interface can be controlled by the GPCM,
UPM, or SDRAM controller. All may exist in the same system.
The GPCM provides a flexible asynchronous interface to SRAM, EPROM, FEPROM, ROM, and other devices such
as asynchronous DSP host interfaces and CAMs. Minimal glue logic is required. Handshake signals can be
configured to transition on fractions of the system clock. The GPCM does not support bursting.
The UPM allows an extremely flexible interface in which the programmer configures each of a set of
general-purpose protocol signals by writing the transition pattern into a memory array. The UPM supports
synchronous and bursting interfaces. It also supports multiplexed addressing so that a simple DRAM interface can
be implemented. The UPM is entirely flexible in order to provide a very high degree of customization with respect
to both asynchronous and burst-synchronous interfaces, which permits glueless or almost glueless connection to
burst SRAM, custom ASIC, and synchronous DSP interfaces.
The LBC provides a synchronous DRAM (SDRAM) machine that supplies the control functions and signals for
glueless connection to JEDEC–compliant SDRAM devices. An internal DLL (delay-locked loop) for bus clock
generation ensures improved data setup margins for board designs. The SDRAM machine can optimize burst
transfers and exploits interleaving to maximize data transfer bandwidth and minimize access latency. Programmable
row and column address multiplexing allows a variety of SDRAM configurations and sizes to be supported without
hardware changes.
3.11 Three-Speed Ethernet Controllers (10/100/1Gb)
The MPC8540 has two on-chip three-speed Ethernet controllers (TSECs). The TSECs incorporate a media access
control sublayer (MAC) that supports 10- and 100-Mbps, and 1-Gbps Ethernet/802.3 networks with MII, GMII,
RGMII, RTBI, and TBI physical interfaces. The TSECs include 2-Kbyte receive and transmit FIFOs, and DMA
functions.
The buffer descriptors are based on the MPC8260 and MPC860T 10/100 programming models.
The MPC8540 TSECs support programmable CRC generation and checking, RMON statistics, and jumbo frames
of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache to speed classification or
other frame processing.
MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1
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Freescale Semiconductor