MPC8540PX667LB Freescale Semiconductor, MPC8540PX667LB Datasheet
MPC8540PX667LB
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MPC8540PX667LB Summary of contents
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... I/O port, and 2 universal asynchronous receiver/transmitters (DUART). The high level of integration in the MPC8540 simplifies board design and offers significant bandwidth and performance. 2 MPC8540 Overview The following section provides a high-level overview of the features of the MPC8540. © Freescale Semiconductor, Inc., 2004. All rights reserved controller, a 4-channel DMA controller, a MPC8540PB ...
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... Fabric 10/100/1Gb 10/100/1Gb Figure 1. MPC8540 Block Diagram e500 Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Cache Cache RapidIO-8 RapidIO Interface 16 Gb/s PCI-X 64b PCI/PCI-X Bus 133 MHz Interface 4-Channel DMA Controller TSEC MII, GMII,TBI, RTBI, RGMII TSEC MII, GMII,TBI, RTBI, RGMII Freescale Semiconductor ...
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... Page mode support ( simultaneous open pages) — Contiguous or discontiguous memory mapping — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self-refresh SDRAM MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor MPC8540 Overview 3 ...
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... Interrupts can be routed to the e500 core’s standard or critical interrupt inputs. — Interrupt summary registers allow fast identification of interrupt source. 2 • controller — Two-wire interface — Multiple master support 2 — Master or slave I C mode support MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 4 Freescale Semiconductor ...
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... MII management interface for control and status — Programmable CRC generation and checking — Ability to force allocation of header information and buffer descriptors into L2 cache MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor MPC8540 Overview 2 C interface ...
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... Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the 8 counters — Supports duration and quantity threshold counting MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 6 Freescale Semiconductor ...
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... The core frequencies are derived from either the primary PCI clock input or an external oscillator. For information regarding the e500 core refer to the following documents: • EREF: A Reference for Freescale Semiconductor Book E and the e500 Core • PowerPC e500 Core Complex Reference Manual • ...
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... MPC8560 and in their derivatives (that is, in all PowerQUICC III devices). However, these instructions will not be supported in devices subsequent to PowerQUICC III. Freescale Semiconductor strongly recommends that use of these instructions be confined to libraries and device drivers. Customer software that uses SPE or SPFP APU instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices ...
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... Easily adaptable to 60x-like environments — Supports one-level pipelining of addresses with address-retry responses • Extended exception handling — Supports Book E interrupt model – Interrupt vector prefix register (IVPR) MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor MPC8540 Architecture Overview 9 ...
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... JTAG interface — ESP support — ABIST for arrays — LBIST • Reliability and serviceability — Internal code parity — Parity checking on e500 local bus MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0 virtual memory physical memory Freescale Semiconductor ...
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... Subsequent to a load miss updating the memory, loads or stores can occur to that line on the very next cycle. MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor MPC8540 Architecture Overview 11 ...
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... The MPC8540 can invoke a level of system power management by asserting the MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode. MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 12 Freescale Semiconductor ...
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... Software programmable baud generators divide the system clock to generate a 16x clock. Serial interface data formats (data length, parity, 1/1.5/2 STOP bit, baud rate) are also software selectable. MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor allows the connection of additional devices to the bus for expansion ...
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... The MPC8540 TSECs support programmable CRC generation and checking, RMON statistics, and jumbo frames 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache to speed classification or other frame processing. MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 14 Freescale Semiconductor ...
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... The physical layer of the RapidIO unit can operate 500 MHz. Because the interface is defined as a source-synchronous, double-data-rate, LVDS-signaling interconnect, the theoretical unidirectional peak bandwidth MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor MPC8540 Architecture Overview 15 ...
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... Both inbound and outbound translation windows are provided. The ATMUs allows the MPC8540 to be part of larger address maps such as the PCI 64-bit address environment and the RapidIO environment. MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 16 Freescale Semiconductor ...
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... The following section provides block diagrams of different MPC8540 applications. The MPC8540 is a very flexible device and can be configured to meet many system application needs. In order to build a system, many factors should be considered. MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor 2 1 MPC8540 Application Examples ...
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... Processor 256K L2 Core Memory Complex Block RapidIO 2x GEnet Memory PCI Control PCI-X 133-MHz Backplane RAID Controller Figure 3 shows an MPC8540 as a ASIC Accelerator Hardware To Network ASIC Forwarding Plane DDR Memory To Control Plane Dual Gigabit Ethernet FPGA ROM GPCM/UPM/ SDRAM RTC/NVRAM Freescale Semiconductor ...
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... MPC8540 in a virtual private network (VPN) access that is enabled through RapidIO and Ethernet. Data In RapidIO High Data Out Bandwidth Aggregators Figure 6. VPN Access Point Enabled by RapidIO and Ethernet MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor DDR Flash Memory Descriptor Memory Disk Cache PCI-X ASIC DDR ...
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... Figure 7. MPC8540 with SERDES Core Complex Unit Local Bus 256K L2 Controller Port Memory Block RapidIO 2x GEnet Memory PCI Control 190 DDR Security Memory 64-Bit PCI 64-Bit Interface 66-MHz PCI Table 1. Document Revision History Substantive Change(s) SERDES Data In 10/100/1Gb Data Out Ethernet Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor Revision History 21 ...
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... Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 22 Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1 Freescale Semiconductor Revision History 23 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...