XS1-L01A-LQ64-C4 XMOS, XS1-L01A-LQ64-C4 Datasheet
XS1-L01A-LQ64-C4
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XS1-L01-LQ64-C4
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XS1-L01A-LQ64-C4 Summary of contents
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... XS1-L1 64LQFP Datasheet Publication Date: 2010/05/20 Copyright © 2010 XMOS Ltd. All Rights Reserved. Version 2.1 ...
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... XS1-L1 64LQFP Datasheet (2.1) 1 Description XS1-L1 Description The XS1- member of the XS1-L family of XMOS de- vices. The XS1-L family blends a powerful programmable fabric based on multi-threaded processors with a high- level programming language design flow. XMOS chips are general-purpose programmable devices that can be used in a wide range of applications and systems. The XS1-L1 device is based on the XMOS XCore™ ...
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... 2.1 XCore Signals The XS1-L1 64 LQFP device provides 36 XCore signals that can be used for generic I/O ports or for XMOS Links. 2.1.1 XCore signals as I/O ports The following table shows the I/O ports available on the XCore processor. Each port is bidirectional. See Section LQFP device ...
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... XS1-L1 64LQFP Datasheet (2.1) 2.1.3 Precedence Ports and XMOS Links are connected to pins on the XS1-L1 by the program running on the device. The ports and links are multiplexed and follow a defined precedence if they overlap on the same core XMOS Link is enabled, the link has access to the pins; the pins of the underlying ports are disabled ...
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... XS1-L1 64LQFP Datasheet (2.1) 2.2 Port Pin Table Package XMOS Links Pin Name Pin ID 5bit X0D0 16 X0D1 15 X0LA4out X0D2 14 X0LA3out X0D3 12 X0LA2out X0D4 11 X0LA1out X0D5 10 X0LA0out X0D6 7 X0LA0in X0D7 5 X0LA1in X0D8 3 X0LA2in X0D9 2 X0LA3in X0D10 1 X0LA4in X0D11 64 X0D12 63 X0D13 62 X0LB4out X0D14 ...
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... XS1-L1 64LQFP Datasheet (2.1) 2.3 System Service Pins Pin ID Signal 9 CLK 17 DEBUG 22 MODE0 23 MODE1 24 MODE2 25 MODE3 2.4 Core Power and Ground Pins Pin ID Signal 4 VDD 13 VDD 21 VDD 28 VDD 37 VDD 43 VDD 52 VDD 61 VDD 2.5 XCore I/O Power Pins Pin ID Signal 6 VDDIO 18 VDDIO ...
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... XS1-L1 64LQFP Datasheet (2.1) 3 System Services System Services are required to support correct device behavior. These signals control clocking, reset and boot behavior of the device. 3.1 Clock control signals These signals control the on-chip PLL of the XS1-L1 Signal Pin ID PLL_AVDD 20 PLL_AGND 19 CLK ...
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... Following a reset the PLL re-establishes lock after which the device boots up according to the boot mode (see MODE). 3.3 SPI Interface When booting the XS1-L1 device from a SPI interface, the SPI device must be connected to the XS1-L1 as follows: Pin Name Pin ID ...
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... XS1-L1 64LQFP Datasheet (2.1) 3.4 JTAG Operation The XS1-L1 device contains a standard 5 pin JTAG interface, which allows the following functionality: Boundary scan testing for verifying printed circuit board connectivity. In-circuit source level debugging of the XCore. Programming of the One Time Programmable (OTP) ROM. ...
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... XS1-L1 64LQFP Datasheet (2. IR_LENGTH = 4 TDI TDI TCK TMS TRST_N 3.4.1 Device identification register The JTAG device identification register can be read by using the IDCODE instruction. Its contents are specified as follows: Bit31 Version 3.4.2 Usercode register The JTAG usercode register can be read by using the USERCODE instruction. Its contents are specifi ...
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... XS1-L1 64LQFP Datasheet (2. and Switching Characteristics 4.1 Operating Conditions Symbol Parameter VDD(IO) I/O DC supply voltage VDD(CORE) Core DC supply voltage AVDD(PLL) PLL analogue supply Cl XCore I/O load capacitance Operating range (Commercial) Ta Operating range (Industrial) Tj Junction temperature Tstg Storage temperature 4.2 DC Characteristics Symbol Parameter ...
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... VDD held at 0V. The VDD supply should then rise to its nominal operating range with a rise time of less than 10ms. 4.5.2 Power Consumption Core power consumption The power consumption of the XS1-L1 is highly application dependant. The following figures should be used for budgetary purposes only: MIN TYP ...
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... For a more detailed analysis see 4.6 Clock XS1-L devices use an input clock frequency, supplied by the user on the CLK pin, to drive the PLL and obtain the system clock. The nominal frequency of the clock for all XS1 family components is 20MHz but other clock frequencies can be used by reprogramming the internal PLL through use of the MODE pins or by application software. For further details on confi ...
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... Assumes typical core and I/O voltages, with nominal activity. 4.7 Memory 4.7.1 Internal static memory The XS1-L1 has a total of 64KBytes of fast internal static memory for high rates of data throughput. Each internal memory access consumes one core clock cycle. There is no dedicated external memory interface, although memory can be expanded through appropriate use of the ports ...
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... ClkBlk The Input Valid window parameter relates to the capability of the XS1-L1 family devices to capture data input to the chip with respect to an external clock source. This parameter can be calculated as the sum of the input setup time and input hold time with regard to the external clock as measured at the L1 device pins. The output invalid window specifi ...
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... XS1-L1 64LQFP Datasheet (2.1) 4.10 JTAG Timing All JTAG operations are synchronous to TCK apart from the global asynchronous reset TRST_N. Parameters TCK frequency (debug) TCK frequency (boundary scan) T SETUP T HOLD T CLOCK to OUT Notes: 1. Timing applies to TMS and TDI inputs 2. Timing applies to TDO output from negative edge of TCK ...
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... XS1-L1 64LQFP Datasheet (2.1) 5 Package Details 5.1 Package Pin Layout The following diagram shows the pin names and locations for the 64 LQFP package. X0D10 1 X0D9 2 X0D8 3 VDD 4 X0D7 5 VDDIO 6 X0D6 7 RST_N 8 CLK 9 X0D5 10 X0D4 11 X0D3 12 VDD 13 X0D2 14 X0D1 15 X0D0 16 GND www.xmos.com ...
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... XS1-L1 64LQFP Datasheet (2.1) 5.2 Package Mechanical Details www.xmos.com 18/24 ...
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... XS1-L1 64LQFP Datasheet (2.1) 5.3 Package Marking Details USMMYYL1 C5 LLLLLL.LL Manufacture Date Code USMMYYL1 USMMYYL1 C5 USMMYYL1 I4 USMMYYL1 I5 Manufacturing Date Code Qualification/Speed(Optional) Lot Code Part Number XS1-L01A-LQ64-C4 XS1-L01A-LQ64-C5 XS1-L01A-LQ64-I4 XS1-L01A-LQ64-I5 www.xmos.com 19/24 ...
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... Part numbering and ordering information XMOS Ident & Architecture Number of XCores Revision Mask (A-Z) Package Type Pin Count Temp Grade (C commercial 0-70C) Speed Grade (4 normal speed) 6.1 Orderable part numbers Part Number Speed XS1-L01A-LQ64-C4 400MIPS XS1-L01A-LQ64-C5 500MIPS XS1-L01A-LQ64-I4 400MIPS XS1-L01A-LQ64-I5 500MIPS XS1 L 01 Family Package 64 pin LQFP 0 ...
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... XS1-L1 64LQFP Datasheet (2.1) 7 Device Configuration Example schematic diagrams detailing minimal system configurations may be found at: http://xmos.com/support/silicon 8 Addendum 8.1 USB ULPI Mode When using the XS1-L1 with ULPI, the ULPI signals must only be connected to the following pins: Pin Name Pin ID X0D12 63 X0D13 ...
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... XS1-L System Specification XMOS Tools User Guide XS1 Assembly Language Manual XMOS XS1 32-Bit Application Binary Interface XS1-L Clock Frequency Control Application Note XS1 Port I/O Timing Application Note XS1-L Link Performance and Design Guidelines Estimating Power Consumption For XS1-L Devices ...
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... Added Industrial and Commercial Qualification values Added 500MHz part Section 3.2, NOTE updated "... the boot mode indicated on the MODE[3:2] pins is ignored." Corrected document title to XS1-L1 64LQFP Datasheet. Added SPI pin details. Added Precedence section. Revised format Added JTAG information ...
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... XS1-L1 64LQFP Datasheet (2.1) 11 Errata To guarantee a logic low is seen on the following pins, the driving circuit should present an impedance of less than 100 ohms to ground. Pin 25, 24, 23 Usually this is not a problem for CMOS drivers driving single inputs, however, if one or more of these inputs are placed in parallel, additional logic buffers may be required to guarantee correct operation ...