MPC8314EVRAGDA Freescale Semiconductor, MPC8314EVRAGDA Datasheet - Page 91
![MPU POWERQUICC II PRO 620-PBGA](/photos/6/78/67806/mpc8314evragda_sml.jpg)
MPC8314EVRAGDA
Manufacturer Part Number
MPC8314EVRAGDA
Description
MPU POWERQUICC II PRO 620-PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8314VRADDA.pdf
(106 pages)
Specifications of MPC8314EVRAGDA
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
16 KB
I/o Voltage
- 0.3 V, + 3.6 V
Interface Type
I2C, SPI
Minimum Operating Temperature
0 C
Number Of Programmable I/os
32
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8314EVRAGDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8314EVRAGDA
Manufacturer:
FREESCALE
Quantity:
20 000
23 Clocking
Figure 60
1
2
Freescale Semiconductor
SD_REF_CLK_B
SD_REF_CLK
125-MHz source
125/100 MHz
USB_CR_CLK_IN
USB_CR_CLK_OUT
SYS_CR_CLK_IN
GTX_CLK125
USB_CLK_IN
SYS_CLK_IN
SYS_CR_CLK_OUT
Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL].
Multiplication factor L = 2, 3, 4 and 5. Value is decided by RCWLR[SPMF].
Crystal
Crystal
CFG_CLKIN
_DIV
shows the internal distribution of clocks within the MPC8314E
MPC8314E PowerQUICC
+
-
Converter
Protocol
eTSEC
USB Mac
USB PHY
PLL
PCVTR Mux
mux
/1,/2
PLL
MPC8314E
PCI Express
x L
System
Converter
SerDes PHY
Figure 60. MPC8314E Clock Subsystem
Protocol
PLL
2
TDM
™
/n
Divider (÷2)
PCI Clock
II Pro Processor Hardware Specifications, Rev. 0
Clock
Unit
csb_clk to rest
of the device
csb_clk
ddr_clk
lbc_clk
To local bus
x M
to DDR
memory
controller
Core PLL core_clk
Sys Ref
1
Clock
Divider
DDR
Clock
Divider
/n
LBC
e300c3 core
1
0
/2
RTC
3
MEMC_MCK
MEMC_MCK
LCLK[0:1]
PCI_CLK_OUT[0:2]
PCI_CLK/
PCI_SYNC_IN
RTC_CLK (32 kHz)
PCI_SYNC_OUT
Local Bus
Memory
Device
DDR
Memory
Device
Clocking
91