mpc8314e Freescale Semiconductor, Inc, mpc8314e Datasheet

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... In addition to the e300 core, the SoC © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8314EEC ™ II Pro Processor 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. MPC8314E Features . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 4. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12 5. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 16 8 ...

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... PowerQUICC processor-based designs for backward compatibility and easier software migration. The MPC8314E also offers peripheral interfaces such as a 32-bit PCI interface with MHz operation, 16-bit enhanced local bus interface with MHz operation, TDM interface, and USB 2 ...

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... Performance monitor 2.2 Serial Interfaces The following interfaces are supported in the MPC8314E. • Two enhanced TSECs (eTSECs) • Two Ethernet interfaces using one RGMII/MII/RMII/RTBI or SGMII (no GMII) 2 • Dual UART, one I C, and one SPI interface 2.3 Security Engine The security engine is optimized to handle all the algorithms associated with IPSec, 802.11i, and iSCSI. ...

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... The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock • Signal (RCK) can be configured as either input or output • Frame sync and data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock MPC8314E PowerQUICC 4 ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

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... Two controllers designed to comply with IEEE Std 802.3™, IEEE 802.3u™, IEEE 802.3x™, IEEE 802.3z™, IEEE 802.3au™, IEEE 802.3ab™, and IEEE Std 1588™ MPC8314E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 MPC8314E Features 5 ...

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... PCI Express-based PME events are not supported 2.12 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the MPC8314E to exchange data between other PowerQUICC family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. ...

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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8314E, which is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but they are included for complete reference. These are not purely I/O buffer design specifications. ...

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... LVDD means LVDD1_OFF and LVDD2_ON 3.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for theMPC8314E. Note that the values in are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic ...

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... I/O supply Analog and digital ground Junction temperature range Note: 1. The NVDDx_ON are static power supplies and can be connected together. 2. The NVDDx_OFF are switchable power supplies and can be connected together. 3. Minimum Temperature is specified with T MPC8314E PowerQUICC Freescale Semiconductor Recommended Symbol 1 Value XPADVSS ...

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... Power Sequencing The MPC8314E does not require the core supply voltage (VDD and VDDC) and I/O supply voltages (GVDD, LVDDx_ON, LVDDx_OFF, NVDDx_ON and NVDDx_OFF applied in any particular order. During the power ramp up, before the power supplies are stable, if the I/O voltages are supplied ...

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... I/O pins, with the exception of wake-up pins, must be turned off. Applying supplied external voltage to any I/O pins, except the wake up pins, while the device warm standby mode may cause permanent damage to the device. MPC8314E PowerQUICC Freescale Semiconductor V 0.7 V 90% ...

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... Typical power is based on a voltage of V MPC8314E PowerQUICC 12 Figure 4 when implemented along with low power D3 Continuous I/O Voltage (LVDDx_ON, NVDDx_ON) Continuous Core Voltage VDDC t SYS_CLK_IN Table 4. MPC8314E Power Dissipation CSB Frequency (MHz) Typical 133 1.116 133 1.142 133 1.167 = 1.05V, a junction temperature ...

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... Internal PHY (UTMI mode) PCIe two 2.5 GHz — x1lane Other I/O — — 5 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8314E. MPC8314E PowerQUICC Freescale Semiconductor Table 5. MPC8314E Power Dissipation LVDD1_OFF/ LVDD2 LVDD2_ON _ON (3 ...

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... USB_CLK_IN input current USB_CR_CLK_IN input current 5.2 AC Electrical Characteristics The primary clock source for the MPC8314E can be one of two inputs, SYS_CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. input (SYS_CLKIN/PCI_CLK) AC timing specifications for the MPC8314E. Table 7. SYS_CLKIN AC Timing Specifications ...

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... This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8314E. 6.1 RESET DC Electrical Characteristics Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8314E. Table 8. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage ...

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... DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8314E. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V. 7.1 DDR and DDR2 SDRAM DC Electrical Characteristics Table 11 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8314E when GVDD(typ ...

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... Delta input/output capacitance: DQ, DQS Note: 1. This parameter is sampled. GVDD = 1.8 V ± 0.090 MHz, T Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8314E when GVDD(typ) = 2.5 V Table 13. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage ...

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... AC input high voltage Table 17 lists the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V. Table 17. DDR SDRAM Input AC Timing Specifications for 2.5 V Interface At recommended operating conditions with GVDD of 2.5V ± 200 mV Parameter AC input low voltage AC input high voltage MPC8314E PowerQUICC 18 Symbol DIO = 25° ...

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... CISKEW Figure 5 shows the DDR SDRAM input AC timing for the tolerated MDQS to MDQ skew (t MCK[n] MCK[n] MDQS[n] MDQ[x] MPC8314E PowerQUICC Freescale Semiconductor Symbol Min t CISKEW 266 MHz –875 200 MHz –1250 )) where T is the clock period and abs(t ...

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... Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t symbol conventions described in note 1. MPC8314E PowerQUICC 20 1 Symbol ...

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... MCK MDQS MDQS Figure 7 shows the DDR and DDR2 SDRAM output timing diagram. MCK MCK ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 7. DDR and DDR2 SDRAM Output Timing Diagram MPC8314E PowerQUICC Freescale Semiconductor t MCK t = 0.6 ns DDKHMH(max –0.6 ns DDKHMH(min) Figure 6. Timing Diagram for t DDKHMH ...

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... The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each sixteenth sample. 9 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8314E PowerQUICC Ω Figure 8. DDR AC Test Load Table 22 ...

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... Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Note: 1. The symbol this case, represents the LV IN MPC8314E PowerQUICC Freescale Semiconductor Section 9.3, “Ethernet Management Symbol Conditions LVDD — — –4.0 mA ...

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... Note that, in general, MTX the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). MPC8314E PowerQUICC 24 Symbol Conditions LVDD — ...

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... For example, the subscript of t MRX used with the appropriate letter: R (rise (fall). Figure 10 provides the AC test load for eTSEC. Output MPC8314E PowerQUICC Freescale Semiconductor t MTX t t MTXH ...

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... RMII transmit timing (RMT) for the time t (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t times, the latter convention is used with the appropriate letter: R (rise (fall). MPC8314E PowerQUICC 26 t MRX ...

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... Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 13 provides the AC test load. Output MPC8314E PowerQUICC Freescale Semiconductor t RMX t t ...

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... This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. GTX_CLK supply voltage is fixed at 3.3V inside the chip. If PHY supplies a 2.5 V Clock signal on this input, set TSCOMOBI bit of System I/O configuration register (SICRH See the MPC8315E PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual . MPC8314E PowerQUICC 28 t RMX ...

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... The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 30. MII Management DC Electrical Characteristics Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage MPC8314E PowerQUICC Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] ...

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... R (rise (fall). 2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the maximum frequency is 4.16 MHz and the minimum frequency is 0.593 MHz). 3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns). MPC8314E PowerQUICC 30 Symbol Conditions ...

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... Input high voltage Input low voltage Input current 9.4.2 1588 Timer AC Specifications Table 33 provides the 1588 timer AC specifications. Parameter Timer clock cycle time Input setup to timer clock Input hold from timer clock MPC8314E PowerQUICC Freescale Semiconductor t MDC t t MDCF MDCH t MDDVKH t MDDXKH ...

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... REFCLK cycle time REF t REFCLK cycle-to-cycle jitter. Difference in the period of any two REFCJ adjacent REFCLK cycles t Phase jitter. Deviation in edge location with respect to mean REFPJ edge location MPC8314E PowerQUICC 32 Symbol t GCLKNV t TMRAL 17, where C is the external (on board) AC-Coupled capacitor. Each TX Figure 48 ...

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... V is also referred to as output common mode voltage The |V | value shown in the Typ column is based on the condition of XCOREVDD 500 mV), SerDes transmitter is terminated with 100-Ω differential load between TX[n] and TX[n]. OS MPC8314E PowerQUICC Freescale Semiconductor . Symbol Min Typ 0.95 VOH — VOL ...

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... Figure 17. 4-Wire AC-Coupled SGMII Serial Link Connection Example MPC8315E SGMII SerDes Interface Transmitter Figure 18. SGMII Transmitter DC Measurement Circuit Table 36. SGMII DC Receiver Electrical Characteristics Parameter Supply Voltage DC Input voltage range Input differential voltage MPC8314E PowerQUICC 34 TXn 50 Ω RXm Ω TXn RXm ...

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... At recommended operating conditions with XCOREVDD = 1.0V ± 5%. Parameter Deterministic Jitter Total Jitter Unit Interval V fall time (80%-20 rise time (20%-80%) OD Notes: 1. Each UI is 800 ps ± 100 ppm. MPC8314E PowerQUICC Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Symbol Min Typ VLOS 30 — 65 — V — ...

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... Each UI is 800 ps ± 100 ppm. 3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs Refer to RapidIO 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications. MPC8314E PowerQUICC 36 Figure 19 shows the SGMII Receiver Input Compliance Symbol ...

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... V /2 RX_DIFFp-p-max 0 Figure 19. SGMII Receiver Input Compliance Mask Figure 20. SGMII AC Test/Measurement Load 10 USB 10.1 USB Dual-Role Controllers This section provides the AC and DC electrical specifications for the USB-ULPI interface. MPC8314E PowerQUICC Freescale Semiconductor 0.275 0.4 0.6 Time (UI) ™ II Pro Processor Hardware Specifications, Rev. 0 USB 1 ...

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... For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 21 and Figure 22 provide the AC test load and signals for the USB, respectively. Output MPC8314E PowerQUICC 38 Table 39. USB DC Electrical Characteristics Symbol ...

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... Input low voltage Table 42 provides the USB clock input (USB_CLK_IN) AC timing specifications. Table 42. USB_CLK_IN AC Timing Specifications Parameter/Condition Frequency range Clock frequency tolerance Reference clock duty cycle Total input jitter/Time interval error MPC8314E PowerQUICC Freescale Semiconductor t USIVKH t t USKHOX USKHOV Figure 22. USB Signals ...

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... NVDD 11.2 Local Bus AC Electrical Specifications Table 44 describes the general timing parameters of the local bus interface of the MPC8314E. Table 44. Local Bus General Timing Parameters Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock ...

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... For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 23 provides the AC test load for the local bus. Output MPC8314E PowerQUICC Freescale Semiconductor 1 Symbol t LBKHOV ...

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... Figure 24. Local Bus Signals, Nonspecial Signals Only LCLK T1 T3 GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8314E PowerQUICC 42 t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBOTOT t ...

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... Table 45 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface. Table 45. JTAG Interface DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8314E PowerQUICC Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t t ...

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... R (rise (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. MPC8314E PowerQUICC 44 Figure 28 Table 2) ...

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... Figure 27 provides the AC test load for TDO and the boundary-scan outputs of the MPC8314E. Output Figure 27. AC Test Load for the JTAG Interface Figure 28 provides the JTAG clock input timing diagram. JTAG External Clock Figure 28. JTAG Clock Input Timing Diagram Figure 29 provides the TRST timing diagram. ...

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... I2KLKV t I2KHKL C I ™ II Pro Processor Hardware Specifications, Rev JTIXKH Input Data Valid Output Data Valid 2 C interface of the MPC8314E. Min Max Unit 0.7 × NVDD NVDD + 0.3 V 0.3 × NVDD –0.3 V 0.2 × NVDD 0 V 0.8 × NVDD NVDD + 0 0.1 × C 250 ...

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... Data hold time: Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) MPC8314E PowerQUICC Freescale Semiconductor Electrical Characteristics (continued) Symbol ...

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... For rise and fall times, the latter convention is used I2C with the appropriate letter: R (rise (fall). 2. MPC8314E provides a hold time of at least 300 ns for the SDA signal (referred to the V undefined region of the falling edge of SCL. 3. The maximum t ...

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... NV IN 14.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8314E is configured as a host or agent device. Table 50 . Table 50. PCI AC Timing Specifications at 66 MHz ...

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... Input timings are measured at the pin. Figure 34 provides the AC test load for PCI. Output Figure 35 shows the PCI input AC timing conditions. CLK Input Figure 35. PCI Input AC Timing Measurement Conditions MPC8314E PowerQUICC 50 1 Symbol Min t — PCKHOV t 2 ...

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... The Differential Output Voltage (or Swing) of the transmitter, V the two complimentary output voltages: V negative. 3. Differential Input Voltage, V The Differential Input Voltage (or Swing) of the receiver, V two complimentary input voltages Differential Peak Voltage, V MPC8314E PowerQUICC Freescale Semiconductor t PCKHOV (or Differential Output Swing): OD – V The V TXn TXn ...

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... TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges OD MPC8314E PowerQUICC – B| Volts. DIFFp DIFFp-p ...

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... XCOREVSS DC exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. MPC8314E PowerQUICC Freescale Semiconductor is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V DIFFp ™ ...

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... SerDes reference clock input requirement for single-ended signaling mode. — To meet the input amplitude requirement, the reference clock inputs might need AC-coupled externally. For the best noise performance, the reference of the clock could be DC MPC8314E PowerQUICC 54 50 Ω ...

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... Figure 41. Single-Ended Reference Clock Input DC Requirements 15.2.3 Interfacing With Other Differential Signaling Levels With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. MPC8314E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 High-Speed Serial Interfaces (HSSI) Vmax < ...

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... SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver’s common mode voltage is higher than the MPC8315E SerDes reference clock input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the MPC8314E PowerQUICC 56 NOTE below are for conceptual reference only ...

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... For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. MPC8314E PowerQUICC Freescale Semiconductor SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK ™ ...

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... Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 Ω to match the transmission line and reduce reflections which are a source of noise to the system. MPC8314E PowerQUICC 58 SD_REF_CLK ...

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... IH 0 –200 IL SDn_REF_CL K minus Figure 46. Differential Measurement Points for Rise and Fall Time SDn_REF_CLK SDn_REF_CLK Figure 47. Single-Ended Measurement Points for Rise and Fall Time Matching MPC8314E PowerQUICC Freescale Semiconductor Symbol Rise Edge Rate Fall Edge Rate V +200 Rise-Fall Matching Figure 46 ...

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... PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8315E. 16.1 DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK For more information, see Section 15.2, “SerDes Reference MPC8314E PowerQUICC 60 RXn TXn 50 Ω 50 Ω TXn RXn Characteristics” ...

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... Symbol Unit interval Differential peak-to-peak V TX-DIFFp-p output voltage De-Emphasized V TX-DE-RATIO differential output voltage (ratio) Minimum TX eye width T TX-EYE MPC8314E PowerQUICC Freescale Semiconductor Comments UI Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations 2*|V TX-DIFFp-p TX- TX-D- ...

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... TX-RCV-DETECT allowed during receiver detection TX DC common mode V TX-DC-CM voltage TX short circuit current I TX-SHORT limit MPC8314E PowerQUICC 62 Comments Jitter is defined as the measurement variation of the crossing points (V TX-DIFFp relation to a recovered TX UI. A recovered calculated over 3500 consecutive unit intervals of sample data. Jitter is ...

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... Transmitter DC Z TX-DC impedance Lane-to-Lane output skew L TX-SKEW AC coupling capacitor C MPC8314E PowerQUICC Freescale Semiconductor Comments Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set After sending an Electrical ...

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... UI in the center of the 3500 UI used for calculating the TX UI recommended that the recovered calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). MPC8314E PowerQUICC 64 Comments This random timeout helps resolve conflicts in crosslink ...

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... Table 55. Differential Receiver (RX) Input Specifications Parameter Symbol Unit interval Differential peak-to-peak V RX-DIFFp-p output voltage Minimum receiver eye T RX-EYE width MPC8314E PowerQUICC Freescale Semiconductor = 0 mV TX-DIFF [Transition Bit 800 mV TX-DIFFp-p-MIN [De-emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0 – ...

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... Electrical idle detect V RX-IDLE-DET-DIFFp-p threshold Unexpected Electrical Idle T RX-IDLE-DET-DIFF- Enter Detect Threshold ENTERTIME Integration Time MPC8314E PowerQUICC 66 Comments Jitter is defined as the measurement variation of the crossing points (V RX-DIFFp relation to a recovered TX UI. A recovered calculated over 3500 consecutive unit intervals of sample data ...

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... The input receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in adequate combination of system simulations and the return loss measured looking into the RX package MPC8314E PowerQUICC Freescale Semiconductor Comments Skew across all lanes on a Link ...

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... The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. MPC8314E PowerQUICC 68 NOTE Figure 51). Note that the series capacitors, C ...

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... Figure 51. Compliance Test/Measurement Load 17 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8314E. 17.1 Timers DC Electrical Characteristics Table 56 provides the DC electrical characteristics for the timers pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 56. Timers DC Electrical Characteristics Characteristic Output high voltage ...

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... GPIO Figure 52 provides the AC test load for the Timers. Output 18 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8314E. 18.1 GPIO DC Electrical Characteristics Table 58 provides the DC electrical characteristics for the GPIO. Table 58. GPIO DC Electrical Characteristics Characteristic Output high voltage ...

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... IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t in edge triggered mode. 20 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8314E. 20.1 SPI DC Electrical Characteristics Table 62 provides the DC electrical characteristics for the SPI ...

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... Figure 54 provides the AC test load for the SPI. Output Figure 55 and Figure 56 represents the AC timing from generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8314E PowerQUICC 72 Symbol Condition I — – ...

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... Output Signals: SPIMOSI (See Note) Note: The clock edge is selectable on SPI. Figure 56. SPI AC Timing in Master Mode (Internal Clock) Diagram 21 TDM This section describes the DC and AC electrical specifications for the TDM of the MPC8314E. 21.1 TDM DC Electrical Characteristics Table 64 provides the DC electrical characteristics TDM. Characteristic ...

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... Use of the rising edge or falling edge as a reference is programmable. TDMxTCK and TDMxRCK are shown using the rising edge. Figure 51 shows the TDM receive signal timing. TDMxRCK t DMIVKH TDMxRD t DMIVKH TDMxRFS TDMxRFS (output) MPC8314E PowerQUICC 74 Table 65. TDM AC Timing specifications Symbol DM_HIGH t DM_LOW t DMIVKH ...

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... TDMxTFS (output) t DMIVKH TDMxTFS (input) 22 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8314E is available in a thermally enhanced plastic ball grid array (TEPBGA II), see MPC8314E TEPBGA II,” and Section 22.2, “Mechanical Dimensions of the TEPBGA II,” on the TEPBGA II. ...

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... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 59. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II 22.3 Pinout Listings Table 66 provides the pin-out listing for the TEPBGA II package. MPC8314E PowerQUICC 76 ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

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... Table 66. MPC8314E TEPBGA II Pinout Listing Signal MEMC_MDQ[0] MEMC_MDQ[1] MEMC_MDQ[2] MEMC_MDQ[3] MEMC_MDQ[4] MEMC_MDQ[5] MEMC_MDQ[6] MEMC_MDQ[7] MEMC_MDQ[8] MEMC_MDQ[9] MEMC_MDQ[10] MEMC_MDQ[11] MEMC_MDQ[12] MEMC_MDQ[13] MEMC_MDQ[14] MEMC_MDQ[15] MEMC_MDQ[16] MEMC_MDQ[17] MEMC_MDQ[18] MEMC_MDQ[19] MEMC_MDQ[20] MEMC_MDQ[21] MEMC_MDQ[22] MEMC_MDQ[23] MEMC_MDQ[24] MEMC_MDQ[25] MEMC_MDQ[26] MEMC_MDQ[27] MEMC_MDQ[28] MEMC_MDQ[29] MEMC_MDQ[30] MPC8314E PowerQUICC Freescale Semiconductor ...

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... Package and Pin Listings Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal MEMC_MDQ[31] MEMC_MDM0 MEMC_MDM1 MEMC_MDM2 MEMC_MDM3 MEMC_MDQS[0] MEMC_MDQS[1] MEMC_MDQS[2] MEMC_MDQS[3] MEMC_MBA[0] MEMC_MBA[1] MEMC_MBA[2] MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MA14 MEMC_MWE MEMC_MRAS MEMC_MCAS ...

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... Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal MEMC_MCKE MEMC_MCK[0] MEMC_MCK[0] MEMC_MCK[1] MEMC_MCK[1] MEMC_MODT[0] MEMC_MODT[1] MEMC_MVREF LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 MPC8314E PowerQUICC Freescale Semiconductor ...

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... Package and Pin Listings Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal LA23 LA24 LA25 LCS[0] LCS[1] LCS[2] LCS[3] LWE[0] /LFWE/LBS LWE[1] LBCTL LALE LGPL0/LFCLE LGPL1/LFALE LGPL2/LFRE/LOE LGPL3/LFWP LGPL4/LGTA/LUPWAIT/LFRB LGPL5 LCLK0 LCLK1 UART_SOUT1/MSRCID0 (DDR ID)/LSRCID0 UART_SIN1/MSRCID1 (DDR ID)/LSRCID1 UART_CTS[1]/MSRCID2 (DDR ID)/LSRCID2 ...

Page 81

... Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal MCP_OUT IRQ[0]/MCP_IN IRQ[1] IRQ[2] IRQ[3] IRQ[4] IRQ[5]/CORE_SRESET_IN IRQ[6] /CKSTOP_OUT IRQ[7]/CKSTOP_IN CFG_CLKIN_DIV EXT_PWR_CTRL PMC_PWR_OK TCK TDI TDO TMS TRST GPIO_18/TDM_RCK GPIO_20/TDM_RD GPIO_19/TDM_RFS GPIO_21/TDM_TCK GPIO_23/TDM_TD GPIO_22/TDM_TFS TEST_MODE QUIESCE MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number ...

Page 82

... Package and Pin Listings Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal HRESET PORESET SYS_XTAL_IN SYS_XTAL_OUT SYS_CLK_IN USB_XTAL_IN USB_XTAL_OUT USB_CLK_IN PCI_SYNC_OUT RTC_CLK PCI_SYNC_IN AVDD1 AVDD2 THERM0 DMA_DACK0/GPIO_13 DMA_DREQ0/GPIO_12 DMA_DONE0/GPIO_14 NC, No Connect NC, No Connect NC, No Connect NC, No Connect NC, No Connect NC, No Connect NC, No Connect ...

Page 83

... Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] MPC8314E PowerQUICC ...

Page 84

... Package and Pin Listings Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal PCI_C/BE[0] PCI_C/BE[1] PCI_C/BE[2] PCI_C/BE[3] PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM M66EN PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_PME GPIO_24/TSEC1_COL/USBDR_TXDRXD0 GPIO_25/TSEC1_CRS/USBDR_TXDRXD1 TSEC1_GTX_CLK/USBDR_TXDRXD2 TSEC1_RX_CLK/USBDR_TXDRXD3 TSCE1_RX_DV/USBDR_TXDRXD4 TSEC1_RXD[3]/USBDR_TXDRXD5 ...

Page 85

... Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal TSEC1_RXD[1]/USBDR_TXDRXD7/TSEC_TMR_CLK TSEC1_RXD[0]/USBDR_NXT/TSEC_TMR_TRIG1 TSEC1_RX_ER/USBDR_DIR/TSEC_TMR_TRIG2 TSEC1_TX_CLK/USBDR_CLK GPIO_28/TSEC1_TXD[3]/TSEC_TMR_GCLK GPIO_29/TSEC1_TXD[2]/TSEC_TMR_PP1 GPIO_30/TSEC1_TXD[1]/TSEC_TMR_PP2 TSEC1_TXD[0]/USBDR_STP/TSEC_TMR_PP3 GPIO_31/TSEC1_TX_EN/TSEC_TMR_ALARM1 TSEC1_TX_ER/TSEC_TMR_ALARM2 TSEC_GTX_CLK125 TSEC_MDC/LB_POR_CFG_BOOT_ECC TSEC_MDIO GPIO_26/TSEC2_COL GPIO_27/TSEC2_CRS TSEC2_GTX_CLK TSEC2_RX_CLK TSCE2_RX_DV TSEC2_RXD[3] TSEC2_RXD[2] TSEC2_RXD[1] TSEC2_RXD[0] TSEC2_RX_ER TSEC2_TX_CLK TSEC2_TXD[3]/CFG_RESET_SOURCE[0] TSEC2_TXD[2]/CFG_RESET_SOURCE[1] ...

Page 86

... Package and Pin Listings Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal TXA TXA RXA RXA TXB TXB RXB RXB SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SDAVDD SD_PLL_TPA_ANA SDAVSS USB_DP USB_DM USB_VBUS USB_TPA USB_RBIAS USB_PLL_PWR3 USB_PLL_GND0 & USB_PLL_GND1 USB_PLL_PWR1 USB_VSSA_BIAS USB_VDDA_BIAS USB_VSSA USB_VDDA ...

Page 87

... Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal GPIO_2/DMA_DONE1/GTM1_TGATE2/GTM2_TGAT E1 GPIO_3/GTM1_TIN3/GTM2_TIN4 GPIO_4/GTM1_TGATE3/GTM2_TGATE4 GPIO_5/GTM1_TOUT3/GTM2_TOUT1 GPIO_6/GTM1_TIN4/GTM2_TIN3 GPIO_7/GTM1_TGATE4/GTM2_TGATE3 GPIO_8/USBDR_DRIVE_VBUS/GTM1_TIN1/GTM2_ TIN2 GPIO_9/USBDR_PWRFAULT/GTM1_TGATE1/GTM2_ TGATE2 GPIO_10/USBDR_PCTL0/GTM1_TOUT2/GTM2_TOU T1 GPIO_11/USBDR_PCTL1/GTM1_TOUT4/GTM2_TOU T3 SPIMOSI/GPIO_15 SPIMISO/GPIO_16 SPICLK SPISEL/GPIO_17 GVDD LVDD1 _OFF LVDD2 _ON NVDD1 _OFF NVDD1 _ON NVDD2 _OFF MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number ...

Page 88

... Package and Pin Listings Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal NVDD2 _ON NVDD3 _OFF NVDD4 _OFF VDD VDDC MPC8314E PowerQUICC 88 Package Pin Number Pin Type L26, N19 U20, V20, V23, V26, W19, Y18, Y26, AA23, AA25, AC20, AC25, AD23, AE25, AG25, ...

Page 89

... Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal VSS XCOREVDD XCOREVSS XPADVDD MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type A3, A27, B3, B12, B24, B28, C6, C8, C13, C17, C21, C23, C26, D2, D7, D15, D18, D20, D22, E4, E6, E11, E24, E26, F8, F12, F14, F17, F20, G3, ...

Page 90

... This pin should USB_VSSA_BIAS through 10K precision resistor. 9. The LB_POR_CFG_BOOT_ECC functionality for this pin is only available in MPC8314E revision 1.1. The LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor enables the ECC by default. To disable the ECC an external strong pull up resistor or a tri-state buffer is needed. ...

Page 91

... Clocking Figure 60 shows the internal distribution of clocks within the MPC8314E MPC8314E USB Mac USB PHY PLL mux USB_CLK_IN USB_CR_CLK_IN Crystal /1,/2 USB_CR_CLK_OUT CFG_CLKIN _DIV SYS_CLK_IN SYS_CR_CLK_IN Crystal SYS_CR_CLK_OUT eTSEC GTX_CLK125 Protocol 125-MHz source Converter PCVTR Mux SD_REF_CLK SD_REF_CLK_B + PLL - 125/100 MHz 1 Multiplication factor 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL]. ...

Page 92

... In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. frequency. MPC8314E PowerQUICC 92 Table 67 specifies which units have a configurable clock ™ ...

Page 93

... If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO Divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 450–750 MHz. MPC8314E PowerQUICC Freescale Semiconductor Table 67. Configurable Clock Units Default Frequency ...

Page 94

... CFG_SYS_CLKIN_DIV 1 at Reset High High High High 1 CFG_SYS_CLKIN_DIV doubles csb_clk if set low. 2 SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8314E PowerQUICC 94 Table 69. System PLL Multiplication Factors System PLL RCWL[SPMF] Multiplication Factor 0000 Reserved 0001 Reserved × 2 0010 × ...

Page 95

... Suggested PLL Configurations To simplify the PLL configurations, the MPC8314E might be separated into two clock domains. The first domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The clock domains are independent, and each of their PLLs are configured separately ...

Page 96

... Thermal (Preliminary) This section describes the thermal specifications of the MPC8314E. 24.1 Thermal Characteristics provides the package thermal characteristics for the 620 29 × TEPBGA II. Table 74 Table 74. Package Thermal Characteristics for TEPBGA II Characteristic Junction to ambient natural convection Junction to ambient natural convection ...

Page 97

... D When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8314E PowerQUICC Freescale Semiconductor ) + P where P DD ...

Page 98

... The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. MPC8314E PowerQUICC 98 ) can be used to determine the junction temperature with a JT × ...

Page 99

... Table 75. Heat Sinks and Junction-to-Case Thermal Resistance of MPC8314E TEPBGA II Heat Sink Assuming Thermal Grease AAVID 9.4 mm Pin Fin AAVID 9.4 mm Pin Fin AAVID 9.4 mm Pin Fin AAVID 9.4 mm Pin Fin AAVID Pin Fin ...

Page 100

... When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board plastic stiffener. Avoid attachment forces which would MPC8314E PowerQUICC 100 408-436-8770 ...

Page 101

... This section provides electrical and thermal design recommendations for successful application of the MPC8314E. 25.1 System Clocking The MPC8314E includes two PLLs. 1. The platform PLL (AVDD2) generates the platform clock from the externally supplied SYS_CLKIN input. The frequency ratio between the platform and SYS_CLKIN is selected using the platform PLL ratio configuration bits as described in Configuration.” ...

Page 102

... Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8314E system, and the MPC8314E itself requires a clean, tightly regulated source of power. Therefore recommended that the system designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, and LVDD pins of the device ...

Page 103

... Output Buffer DC Impedance The MPC8314E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to NVDD 0 or GND ...

Page 104

... Configuration Pin Multiplexing The MPC8314E provides the user with power-on configuration options that can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...

Page 105

... PVR = 8085_0020 for all devices and revisions in this table. 27 Document Revision History Table 79 provides a revision history for this hardware specification. Revision Date 0 05/2009 Initial public release. MPC8314E PowerQUICC Freescale Semiconductor Table 77. Part Numbering Nomenclature VR C Temperature Package 3 Range Blank = 0 to 105°C VR – ...

Page 106

... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8314EEC Rev. 0 05/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...