MPC885VR133 Freescale Semiconductor, MPC885VR133 Datasheet - Page 72

• Manufacturer Part Number: MPC885VR133
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC Ir

Specifications of MPC885VR133

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• I/o Voltage: 5 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Program Memory Size: 8 KB
• Program Memory Type: EPROM/Flash
• Core Size: 32 Bit
• Cpu Speed: 133MHz
• Embedded Interface Type: I2C, JTAG, SPI, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Rohs Compliant: Yes
• For Use With: CWH-PPC-885XN-VX - BOARD EVAL QUICCSTART MPC885CWH-PPC-885XN-VE - BOARD EVAL QUICCSTART MPC885
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FEC Electrical Characteristics
Figure 73
15.2
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. The
RMII transmitter functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%.
There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency
Table 35
72
M20_RMII
M21_RMII
Num
M5
M6
M7
M8
provides information on the MII and RMII transmit signal timing.
MII_RXD[3:0] (Inputs)
MII and Reduced MII Transmit Signal Timing
shows MII receive signal timing.
MII_RX_CLK (Input)
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup
RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising
edge
MII_TX_CLK and RMII_REFCLK pulse width high
MII_TX_CLK and RMII_REFCLK pulse width low
MII_RX_ER
MII_RX_DV
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
–
1%.
Figure 73. MII Receive Signal Timing Diagram
Table 35. MII Transmit Signal Timing
Characteristic
M1
M2
M3
M4
35%
35%
Min
—
5
4
2
Max
65%
65%
25
—
—
—
Freescale Semiconductor
MII_TX_CLK or
MII_TX_CLK or
RMII_REFCLK
RMII_REFCLK
period
period
Unit
ns
ns
ns
ns