MPC8347VVAGDB Freescale Semiconductor, MPC8347VVAGDB Datasheet - Page 44

• Manufacturer Part Number: MPC8347VVAGDB
• Description: IC MPU POWERQUICC II 672-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347VVAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG
Figure 28
Figure 29
Figure 30
44
provides the TRST timing diagram.
provides the boundary-scan timing diagram.
provides the test access port timing diagram.
External Clock
External Clock
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Data Outputs
Data Outputs
Data Inputs
TDI, TMS
Boundary
Boundary
Boundary
TRST
JTAG
JTAG
TDO
TDO
t
t
Output Data Valid
Output Data Valid
JTKLOX
JTKLDX
Figure 30. Test Access Port Timing Diagram
Figure 29. Boundary-Scan Timing Diagram
Figure 28. TRST Timing Diagram
VM
t
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
VM
VM = Midpoint Voltage (OV DD /2)
t
VM
JTKLOZ
JTKLDZ
t
t
JTKLOV
JTKLDV
t
TRST
t
t
JTDVKH
JTIVKH
VM
Output Data Valid
Output Data Valid
Data Valid
Data Valid
Input
Input
VM
VM
t
t
JTIXKH
JTDXKH
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