EZ80L92AZ050EC00TR Zilog, EZ80L92AZ050EC00TR Datasheet - Page 143
EZ80L92AZ050EC00TR
Manufacturer Part Number
EZ80L92AZ050EC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050EC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ050EC00T
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PS013014-0107
SPI Transmit Shift Register
The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data onto
the SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly
into the shift register for transmission. A Write to this register within an SPI device
configured as a master initiates transmission of the byte of the data loaded into the register.
At the completion of transmitting a byte of data, the SPIF status bit (SPI_SR[7]) is set to 1
in both the master and slave devices.
The SPI Transmit Shift Write-Only register shares the same address space as the SPI
Receive Buffer Read-Only register. See
Table 73. SPI Transmit Shift Register (SPI_TSR = 00BCh)
SPI Receive Buffer Register
The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive data from
the serial bus. The SPIF bit must be cleared prior to a second transfer of data from the shift
register or an overrun condition exists. In cases of overrun, the byte that caused the over-
run is lost.
The SPI Receive Buffer Read-Only register shares the same address space as the SPI
Transmit Shift Write-Only register. See
Table 74. SPI Receive Buffer Register (SPI_RBR = 00BCh)
Bit
Reset
CPU Access
Note: W= Write Only.
Bit
Position
[7:0]
TX_DATA
Bit
Reset
CPU Access
Note: R = Read Only
00h–FFh SPI transmit data.
Value
W
X
X
R
7
7
Description
W
X
X
R
6
6
Table
Table
W
R
X
X
5
5
74.
73.
W
R
X
X
4
4
W
R
X
X
3
3
Product Specification
Serial Peripheral Interface
W
R
X
X
2
2
eZ80L92 MCU
W
X
X
R
1
1
W
X
X
R
0
0
137
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