MC68HC000EI16 Freescale Semiconductor, MC68HC000EI16 Datasheet
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MOTOROLA Microprocessors User’s Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume ...
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Paragraph Number 1.1 MC68000..................................................................................................... 1-1 1.2 MC68008..................................................................................................... 1-2 1.3 MC68010..................................................................................................... 1-2 1.4 MC68HC000................................................................................................ 1-2 1.5 MC68HC001................................................................................................ 1-3 1.6 MC68EC000 ................................................................................................ 1-3 2.1 Programmer's Model ................................................................................... 2-1 2.1.1 User's Programmer's Model .................................................................... 2-1 2.1.2 Supervisor Programmer's Model ............................................................. 2-2 2.1.3 Status ...
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TABLE OF CONTENTS (Continued) Paragraph Number 4.1 Data Transfer Operations............................................................................. 4-1 4.1.1 Read Operations ...................................................................................... 4-1 4.1.2 Write Cycle ............................................................................................... 4-3 4.1.3 Read-Modify-Write Cycle.......................................................................... 4-5 4.2 Other Bus Operations............................................................................... 4-8 5.1 Data Transfer Operations............................................................................ 5-1 5.1.1 Read Operations ..................................................................................... 5-1 ...
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TABLE OF CONTENTS (Continued) Paragraph Number 6.2.4 Exception Stack Frames.......................................................................... 6-9 6.2.5 Exception Processing Sequence ............................................................ 6-11 6.3 Processing of Specific Exceptions ............................................................. 6-11 6.3.1 Reset ...................................................................................................... 6-11 6.3.2 Interrupts ................................................................................................ 6-12 6.3.3 Uninitialized Interrupt .............................................................................. 6-13 6.3.4 Spurious Interrupt ...
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TABLE OF CONTENTS (Continued) Paragraph Number 8.1 Operand Effective Address Calculation Times ........................................... 8-1 8.2 Move Instruction Execution Times .............................................................. 8-2 8.3 Standard Instruction Execution Times ........................................................ 8-3 8.4 Immediate Instruction Execution Times ...................................................... 8-4 8.5 Single Operand Instruction Execution ...
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TABLE OF CONTENTS (Continued) Paragraph Number 10.9 MC68008 AC Electrical Specifications—Clock Timing ............................. 10-9 10.10 AC Electrical Specifications—Read and Write Cycles ............................ 10-10 10.11 AC Electrical Specifications—MC68000 To M6800 Peripheral............... 10-15 10.12 AC Electrical Specifications—Bus Arbitration ......................................... 10-17 10.13 MC68EC000 ...
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Figure Number 2-1 User Programmer's Model ................................................................................... 2-2 2-2 Supervisor Programmer's Model Supplement ..................................................... 2-2 2-3 Supervisor Programmer's Model Supplement (MC68010) .................................. 2-3 2-4 Status Register .................................................................................................... 2-3 2-5 Word Organization In Memory ............................................................................. 2-6 2-6 Data Organization In Memory ...
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LIST OF ILLUSTRATIONS (Continued) Figure Number 5-15 3-Wire Bus Arbitration Timing Diagram (NA to 48-Pin MC68008 and MC68EC000 ........................................................ 5-13 5-16 2-Wire Bus Arbitration Timing Diagram.............................................................. 5-14 5-17 External Asynchronous Signal Synchronization ................................................. 5-16 5-18 Bus Arbitration Unit State Diagrams................................................................... ...
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LIST OF ILLUSTRATIONS (Concluded) Figure Number 10-7 Bus Arbitration Timing...................................................................................... 10-18 10-8 Bus Arbitration Timing...................................................................................... 10-19 10-9 Bus Arbitration Timing—Idle Bus Case ............................................................ 10-20 10-10 Bus Arbitration Timing—Active Bus Case........................................................ 10-21 10-11 Bus Arbitration Timing—Multiple Bus Request ................................................ 10-22 10-12 ...
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Table Number 2-1 Data Addressing Modes ....................................................................................... 2-4 2-2 Instruction Set Summary .................................................................................... 2-11 3-1 Data Strobe Control of Data Bus.......................................................................... 3-5 3-2 Data Strobe Control of Data Bus (MC68008)....................................................... 3-5 3-3 Function Code Output .......................................................................................... 3-9 3-4 Signal Summary ...
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LIST OF TABLES (Concluded) Table Number 8-5 Standard Instruction Execution Times ................................................................. 8-4 8-6 Immediate Instruction Execution Times ............................................................... 8-5 8-7 Single Operand Instruction Execution Times ....................................................... 8-6 8-8 Shift/Rotate Instruction Execution Times ............................................................. 8-6 8-9 Bit Manipulation Instruction Execution ...
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SECTION 1 OVERVIEW This manual includes hardware details and programming information for the MC68000, the MC68HC000, the MC68HC001, the MC68008, the MC68010, and the MC68EC000. For ease of reading, the name M68000 MPUs will be used when referring to all ...
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MC68000 The MC68000 is the first implementation of the M68000 16/-32 bit microprocessor architecture. The MC68000 has a 16-bit data bus and 24-bit address bus while the full architecture provides for 32-bit address and data buses completely ...
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MC68HC000 The primary benefit of the MC68HC000 is reduced power consumption. The device dissipates an order of magnitude less power than the HMOS MC68000. The MC68HC000 is an implementation of the M68000 16/-32 bit microprocessor architecture. The MC68HC000 has ...
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SECTION 2 INTRODUCTION The section provide a brief introduction to the M68000 microprocessors (MPUs). Detailed information on the programming model, data types, addressing modes, data organization and instruction set can be found in M68000PM/AD, M68000 Programmer's Reference Manual . All ...
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Figure 2-1. User Programmer's Model (MC68000/MC68HC000/MC68008/MC68010) 2.1.2 Supervisor Programmer's Model The supervisor programmer's model consists of supplementary registers used in the supervisor mode. The M68000 MPUs contain identical supervisor mode register resources, which are shown in Figure ...
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The SFC and DFC registers allow the supervisor to access user data space or emulate CPU space cycles Figure 2-3. Supervisor Programmer's Model Supplement 2.1.3 Status Register The status register (SR),contains the interrupt mask (eight levels available) ...
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In addition, operations on other data types, such as memory addresses, status word data, etc., are provided in the instruction set. The 14 flexible addressing modes, shown in Table 2-1, include six basic types: 1. Register Direct 2. Register Indirect ...
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Table 2-1. Data Addressing Modes Register Direct Addressing Data Register Direct Address Register Direct Absolute Data Addressing Absolute Short Absolute Long Program Counter Relative Addressing Relative with Offset Relative with Index and Offset Register Indirect Addressing Register Indirect Postincrement Register ...
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When a data register is used as either a source or a destination operand, only the appropriate low-order portion is changed; the remaining high-order portion is neither used nor changed. 2.3.2 Address Registers Each address register (and the stack pointer) ...
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MSB MSB EVEN BYTE MSB LONG WORD 0 LONG WORD 1 LONG WORD MSB ADDRESS 0 ADDRESS 1 ADDRESS 2 MSB = MOST ...
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BYTE 0 BYTE 1 BYTE 0 BYTE 1 1 LONG WORD = 2 WORDS = 4 BYTES = 32 BITS BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 0 BYTE 1 BYTE 2 BYTE 3 Figure 2-7. ...
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Notation for operands: PC — Program counter SR — Status register V — Overflow condition code Immediate Data — Immediate data from the instruction Source — Source contents Destination — Destination contents Vector — Location of exception vector +inf — ...
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The source operand is shifted or rotated by the number of Notation for single-operand operations: ~<operand> — The operand is logically complemented <operand>sign-extended — The operand is sign-extended, all bits of the upper <operand>tested — ...
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Table 2-2. Instruction Set Summary (Sheet Opcode ABCD Source 10 + Destination ADD Source + Destination ADDA Source + Destination ADDI Immediate Data + Destination ADDQ Immediate Data + Destination ADDX Source + Destination ...
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Table 2-2. Instruction Set Summary (Sheet Opcode DIVS Destination/Source DIVU Destination/Source EOR Source Destination EORI Immediate Data Destination EORI to CCR Source CCR CCR EORI supervisor state then Source SR else TRAP EXG Rx ...
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Table 2-2. Instruction Set Summary (Sheet Opcode MOVE USP If supervisor state then USP else TRAP MOVEC If supervisor state then else TRAP MOVEM Registers Destination Source Registers MOVEP Source ...
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Table 2-2. Instruction Set Summary (Sheet Opcode RTE If supervisor state then (SP) SR SP; restore state and deallocate stack according to (SP) else TRAP RTR (SP) CCR ...
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SECTION 3 SIGNAL DESCRIPTION This section contains descriptions of the input and output signals. The input and output signals can be functionally organized into the groups shown in Figure 3-1 (for the MC68000, the MC68HC000 and the MC68010), Figure 3-2 ...
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PROCESSOR STATUS MC6800 PERIPHERAL CONTROL SYSTEM CONTROL Figure 3-2. Input and Output Signals PROCESSOR STATUS SYSTEM CONTROL Figure 3-3. Input and Output Signals 3-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL V CC (2) ADDRESS GND(2) BUS CLK DATA BUS AS R/W ...
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PROCESSOR STATUS MC6800 PERIPHERAL CONTROL SYSTEM CONTROL Figure 3-4. Input and Output Signals (MC68008, 48-Pin Version) PROCESSOR STATUS MC6800 PERIPHERAL CONTROL SYSTEM CONTROL Figure 3-5. Input and Output Signals (MC68008, 52-Pin Version) 3.1 ADDRESS BUS (A23–A1) This 23-bit, unidirectional, three-state ...
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Address Bus (A23–A0) This 24-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data. This bus provides the address for bus operation during all cycles except interrupt acknowledge cycles and breakpoint cycles. During interrupt acknowledge cycles, address lines ...
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Table 3-1. Data Strobe Control of Data Bus UDS High Low High Low Low High Low *These conditions are a result of current implementation and may not appear on future devices. DS Data Strobe ( ) (MC68008) This three-state signal ...
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BR Bus Request ( ). This input can be wire-ORed with bus request signals from all other devices that could be bus masters. This signal indicates to the processor that some other device needs to become the bus master. Bus ...
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SYSTEM CONTROL The system control inputs are used to reset the processor, to halt the processor, and to signal a bus error to the processor. The outputs reset the external devices in the system and signal a processor error ...
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M6800 PERIPHERAL CONTROL These control signals are used to interface the asynchronous M68000 processors with the synchronous M6800 peripheral devices. These signals are described in the following paragraphs. Enable (E) This signal is the standard enable signal common to ...
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Table 3-3. Function Code Outputs Function Code Output FC2 Low Low Low Low High High High High 3.9 CLOCK (CLK) The clock input is a TTL-compatible signal that is internally buffered for development of the internal clocks needed by the ...
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SIGNAL SUMMARY Table 3-4 summarizes the signals discussed in the preceding paragraphs. Signal Name Address Bus Data Bus Address Strobe Read/Write Data Strobe Upper and Lower Data Strobes Data Transfer Acknowledge Bus Request Bus Grant Bus Grant Acknowledge Interrupt ...
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SECTION 4 8-BIT BUS OPERATION The following paragraphs describe control signal and bus operation for 8-bit operation during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. The 8-bit bus operations devices are the MC68008, MC68HC001 ...
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BUS MASTER ADDRESS THE DEVICE 1) SET R/W TO READ 2) PLACE FUNCTION CODE ON FC2–FC0 3) PLACE ADDRESS ON A23-A0 4) ASSERT ADDRESS STROBE (AS) 5) ASSERT LOWER DATA STROBE (LDS) (DS ON MC68008) ACQUIRE THE DATA 1) LATCH ...
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A bus cycle consists of eight states. The various signals are asserted during specific states of a read cycle, as follows: STATE 0 The read cycle starts in state 0 (S0). The processor places valid function codes on FC0–FC2 and ...
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BUS MASTER ADDRESS THE DEVICE 1) PLACE FUNCTION CODE ON FC2–FC0 2) PLACE ADDRESS ON A23–A0 3) ASSERT ADDRESS STROBE (AS) 4) SET R/W TO WRITE 5) PLACE DATA ON D0–D7 6) ASSERT LOWER DATA STROBE (LDS TERMINATE ...
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The descriptions of the eight states of a write cycle are as follows: STATE 0 The write cycle starts in S0. The processor places valid function codes on FC2–FC0 and drives R/W high (if a preceding write cycle has left ...
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BUS MASTER ADDRESS THE DEVICE 1) SET R/W TO READ 2) PLACE FUNCTION CODE ON FC2–FC0 3) PLACE ADDRESS ON A23–A0 4) ASSERT ADDRESS STROBE (AS) 5) ASSERT LOWER DATA STROBE (LDS) (DS ON MC68008) ACQUIRE THE DATA 1) LATCH ...
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CLK FC2–FC0 A23– LDS R/W DTACK D7–D0 Figure 4-6. Read-Modify-Write Cycle Timing Diagram The descriptions of the read-modify-write cycle states are as follows: STATE 0 The read cycle starts in ...
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STATE 12 The write portion of the cycle starts in S12. The valid function codes on FC2–FC0, the address bus lines, AS, and R/W remain unaltered. STATE 13 During S13, no bus signals are altered. STATE 14 On the rising ...
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SECTION 5 16-BIT BUS OPERATION The following paragraphs describe control signal and bus operation for 16-bit bus operations during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. The 16-bit bus operation devices are the MC68000, ...
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BUS MASTER ADDRESS THE DEVICE 1) SET R/W TO READ 2) PLACE FUNCTION CODE ON FC2–FC0 3) PLACE ADDRESS ON A23–A1 4) ASSERT ADDRESS STROBE (AS) 5) ASSERT UPPER DATA STROBE (UDS) AND LOWER DATA STROBE (LDS) ACQUIRE THE DATA ...
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CLK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D8 D7–D0 READ Figure 5-3. Read and Write-Cycle Timing Diagram ...
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A bus cycle consists of eight states. The various signals are asserted during specific states of a read cycle, as follows: STATE 0 The read cycle starts in state 0 (S0). The processor places valid function codes on FC0–FC2 and ...
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The word and byte write-cycle timing diagram and flowcharts in Figures 5-5, 5-6, and 5-7 applies directly to the MC68000, the MC68HC000, the MC68HC001 (in 16-bit mode), the MC68EC000 (in 16-bit mode), and the MC68010. BUS MASTER ADDRESS THE DEVICE ...
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CLK FC2–FC0 A23– UDS LDS R/W DTACK D15–D8 D7–D0 *INTERNAL SIGNAL ONLY WORD ...
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STATE 7 On the falling edge of the clock entering S7, the processor negates AS, UDS, or LDS. As the clock rises at the end of S7, the processor places the address and data buses in the high-impedance state, and ...
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CLK A23–A1 AS UDS OR LDS R/W DTACK D15–D8 FC2–FC0 Figure 5-9. Read-Modify-Write Cycle Timing Diagram The descriptions of the read-modify-write cycle states are as follows: STATE 0 The read cycle starts in ...
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STATE 12 The write portion of the cycle starts in S12. The valid function codes on FC2–FC0, the address bus lines, AS, and R/W remain unaltered. STATE 13 During S13, no bus signals are altered. STATE 14 On the rising ...
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The interrupt acknowledge cycle places the level of the interrupt being acknowledged on address bits A3–A1 and drives all other address lines high. The interrupt acknowledge cycle reads a vector number when the interrupting device places a vector number on ...
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The breakpoint acknowledge cycle is performed by the MC68010 to provide an indication to hardware that a software breakpoint is being executed when the processor executes a breakpoint (BKPT) instruction. The processor neither accepts nor sends data during this cycle, ...
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PROCESSOR GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) TERMINATE ARBITRATION 1) NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) REARBITRATE OR RESUME PROCESSOR OPERATION Figure 5-13. 3-Wire Bus Arbitration Cycle Flowchart (Not Applicable to 48-Pin MC68008 or MC68EC000) ...
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PROCESSOR GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) ACKNOWLEDGE RELEASE OF BUS MASTERSHIP 1) NEGATE BUS GRANT (BG) REARBITRATE OR RESUME PROCESSOR OPERATION Figure 5-14. 2-Wire Bus Arbitration Cycle Flowchart CLK FC2–FC0 A23–A1 AS LDS/ UDS R/W DTACK D15–D0 ...
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CLK FC2–FC0 A19– R/W DTACK D7– PROCESSOR DMA DEVICE Figure 5-16. 2-Wire Bus Arbitration Timing Diagram The timing diagram in Figure 5-15 shows that the bus request is ...
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When no acknowledge is received before the bus request signal is negated, the processor continues the use of the bus. 5.2.2 Receiving The Bus Grant The processor asserts BG as soon as possible. Normally, this process immediately ...
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INTERNAL SIGNAL VALID EXTERNAL SIGNAL SAMPLED BR (EXTERNAL) BR (iNTERNAL) Figure 5-17. External Asynchronous Signal Synchronization Bus arbitration control is implemented with a finite-state machine. State diagram (a) in Figure 5-18 applies to all processors using 3-wire bus arbitration and ...
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STATE STATE Bus Request Internal A = Bus Grant Acknowledge Internal G = Bus Grant T = Three-state Control to Bus Control Logic X = Don't Care Figure 5-18. ...
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BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-19. 3-Wire Bus Arbitration Timing Diagram—Processor Active ...
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BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 ...
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BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-21. 3-Wire Bus Arbitration Timing Diagram—Special Case 5-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...
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BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-22. 2-Wire Bus Arbitration Timing Diagram—Processor Active ...
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BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 ...
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BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-24. 2-Wire Bus Arbitration Timing Diagram—Special Case 5.4. BUS ERROR AND HALT OPERATION ...
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The MC68010 also differs from the other microprocessors described in this manual regarding bus errors. The MC68010 can detect a late bus error signal asserted within one clock cycle after the assertion of data transfer acknowledge. When receiving a bus ...
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S0 S2 CLK FC2–FC0 A23–A1 AS UDS/LDS R/W DTACK D15–D0 BERR HALT READ CYCLE Figure 5-26. Delayed Bus Error Timing Diagram (MC68010) After the aborted bus cycle is terminated and BERR is negated, the processor enters exception processing for the ...
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In the MC68010 read-modify-write operation terminates in a bus error, the processor reruns the entire read-modify-write operation when the RTE instruction at the end of the bus error handler returns control to the instruction in error. The processor ...
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CLK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D0–D15 BERR HALT READ Figure 5-28. Delayed Retry Bus Cycle Timing Diagram The processor terminates the bus cycle, then puts the address and data lines in the high- impedance ...
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CLK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D0–D15 BERR HALT READ Figure 5-29. Halt Operation Timing Diagram While the processor is halted, the address bus and the data bus signals are placed in the high-impedance state. ...
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A double bus fault occurs during a reset operation when a bus error occurs while the processor is reading the vector table (before the first instruction is executed). The reset operation is described in the following paragraph. 5.5 RESET OPERATION ...
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Since the processor asserts the RESET signal for 124 clock cycles during execution of a reset instruction, an external reset should assert RESET for at least 132 clock periods. 5.6 THE RELATIONSHIP OF To ...
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Table 5-1. Asserted on Case Control Rising Edge No. Signal of State N N+2 1 DTACK A S BERR NA NA HALT DTACK NA NA BERR A/S S HALT 3 DTACK X X BERR A ...
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For an MC68010, return DTACK before data verification. If data is invalid, assert BERR on the next clock cycle (case 4). Table 5-6. Conditions of Termination in Table 4-4 Control Signal Bus Error BERR HALT Rerun BERR HALT Rerun ...
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ADDR AS R/W UDS/LDS DATA DTACK Figure 5-32. Fully Asynchronous Write Cycle In the asynchronous mode, the accessed device operates independently of the frequency and phase of the system clock. For example, the MC68681 dual universal asynchronous receiver/transmitter (DUART) does ...
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ADDR AS 17 R/W UDS/LDS DATA DTACK Figure 5-33. Pseudo-Asynchronous Read Cycle During a write cycle, after the processor asserts AS but before driving the data bus, the processor drives R/W low. Parameter #55 specifies the minimum time between the ...
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ADDR AS R/W UDS/LDS DATA DTACK Figure 5-34. Pseudo-Asynchronous Write Cycle In the MC68010, the BERR signal can be delayed after the assertion of DTACK. Specification #48 is the maximum time between assertion of DTACK and assertion of BERR. If ...
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R/W beyond the initiation of the read cycle. STATE 1 Entering S1, a low period of the clock, the address of the accessed device is driven externally with an assertion delay ...
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On the rising edge of the clock, at the end of S7 (which may be the start of S0 for the next bus cycle), the processor places the address bus in the high-impedance state. During a write cycle, the processor ...
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S0 CLOCK 6 ADDR AS UDS/LDS 18 R/W DTACK DATA Figure 5-36. Synchronous Write Cycle A key consideration when designing in a synchronous environment is the timing for the assertion of DTACK and BERR by an external device. To properly ...
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Parameter #47 of Section 10 Electrical Characteristics is the asynchronous input setup time. Signals that meet parameter #47 are guaranteed to be recognized at the next falling edge of the system clock. However, signals that do not meet parameter #47 ...
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SECTION 6 EXCEPTION PROCESSING This section describes operations of the processor outside the normal processing associated with the execution of instructions. The functions of the bits in the supervisor portion of the status register are described: the supervisor/user bit, the ...
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The privilege mode is a mechanism for providing security in a computer system. Programs should access only their own code and data areas and should be restricted from accessing information that they do not need and must not modify. The ...
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Therefore, when instruction execution resumes at the address specified to process the exception, the processor is in the supervisor privilege mode. The transition from supervisor to user mode can be accomplished by any of four instructions: return from ...
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EXCEPTION PROCESSING The processing of an exception occurs in four steps, with variations for different exception causes: 1. Make a temporary copy of the status register and set the status register for exception processing. 2. Obtain the exception vector. ...
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D15 IGNORED Where the MSB of the vector number v0 is the LSB of the vector number Figure 6-2. Peripheral Vector Number Format A31 ALL ZEROES Figure 6-3. Address Translated from 8-Bit Vector Number (MC68000, MC68HC000, MC68HC001, MC68EC000, ...
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The internal exceptions are generated by instructions, address errors, or tracing. The trap (TRAP), trap on overflow (TRAPV), check ...
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Table 6-2. Exception Vector Assignment Vectors Numbers Hex Decimal ...
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Multiple Exceptions These paragraphs describe the processing that occurs when multiple exceptions arise simultaneously. Exceptions can be grouped by their occurrence and priority. The group 0 exceptions are reset, bus error, and address error. These exceptions cause the instruction ...
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Table 6-3. Exception Grouping and Priority Group Exception 0 Reset Address Error Bus Error 1 Trace Interrupt Illegal Privilege 2 TRAP, TRAPV, CHK Zero Divide 6.2.4 Exception Stack Frames Exception processing saves the most volatile portion of the current processor ...
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SSP Figure 6-5. Group 1 and 2 Exception Stack Frame (MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008 FORMAT 6-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL EVEN BYTE ODD BYTE 0 7 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER ...
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Format Code 6.2.5 Exception Processing Sequence In the first step of exception processing, an internal copy is made of the status register. After the copy is made, the S bit of the status register is set, putting the processor into ...
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In the MC68010, the VBR is forced to zero. The vector number is internally generated to reference the reset exception vector at location 0 in the supervisor program space. Because no assumptions ...
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The offset value in the format/offset word on the MC68010 is the vector number multiplied by four. The format is all zeros. The saved value of the program counter is the address of the instruction ...
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A signed divide (DIVS) or unsigned divide (DIVU) instruction forces an exception if a division operation is attempted with a divisor of zero. 6.3.6 Illegal and Unimplemented Instructions Illegal instruction is the term used to refer to any of the ...
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Privilege Violations To provide system security, various instructions are privileged. An attempt to execute one of the privileged instructions while in the user mode causes an exception. The privileged instructions are as follows: AND Immediate to SR EOR Immediate ...
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After the execution of the instruction is complete and before the start of the next instruction, exception processing for a trace begins. A copy is made of the status register. The transition to supervisor mode is made, and the T ...
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Only an external reset operation can restart a halted processor LOWER ADDRESS ACCESS ADDRESS PROGRAM COUNTER R/W (Read/Write): Write=0, Read=1. I/N (Instruction/Not): Instruction=0, Not=1 Figure 6-7. Supervisor Stack Order for Bus ...
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SP 1000 NOTE: The stack pointer is decremented by 29 words, although only 26 words of information are actually written to memory. The three additional words are reserved for future use by Motorola. . ...
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Figure 6-9. If the bus cycle is a read, the data at the fault address should be written to the images of the data input buffer, instruction input buffer, or both according to the data fetch (DF) and ...
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RETURN FROM EXCEPTION (MC68010) In addition to returning from any exception handler routine on the MC68010, the RTE instruction resumes the execution of a suspended instruction by returning to the normal processing state after restoring all of the temporary ...
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SECTION 7 8-BIT INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock (CLK) periods for the MC68008 and MC68HC001/MC68EC000 in 8-bit mode. In this data assumed that both memory read ...
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Table 7-1. Effective Address Calculation Times Addressing Mode Dn Data Register Direct An Address Register Direct (An) Address Register Indirect (An)+ Address Register Indirect with Postincrement –(An) Address Register Indirect with Predecrement ( An) Address Register Indirect with ...
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Table 7-3. Move Word Instruction Execution Times Source 8(2/0) 8(2/0) An 8(2/0) 8(2/0) (An) 16(4/0) 16(4/0) (An)+ 16(4/0) 16(4/0) –(An) 18(4/0) 18(4/ An) 24(6/0) 24(6/ An, Xn)* 26(6/0) 26(6/0) (xxx).W 24(6/0) ...
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In Table 7-5, the following notation applies: An — Address register operand Dn — Data register operand ea — An operand specified by an effective address M — Memory effective address operand Table 7-5. Standard Instruction Execution Times Instruction ADD/ADDA ...
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The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). ...
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Table 7-7. Single Operand Instruction Instruction CLR NBCD NEG NEGX NOT Scc TAS TST +Add effective address calculation time. 7.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES Table 7-8 lists the timing data for the shift and rotate instructions. The total number of ...
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BIT MANIPULATION INSTRUCTION EXECUTION TIMES Table 7-9 lists the timing data for the bit manipulation instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described ...
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JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES Table 7-11 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective address (LEA), push effective address (PEA), and move multiple registers (MOVEM) instructions. The total ...
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Table 7-12. Multiprecision Instruction Instruction ADDX CMPM SUBX ABCD SBCD 7.11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES Tables 7-13 and 7-14 list the timing data for miscellaneous instructions. The total number of clock periods, the number of read cycles, and the number ...
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Table 7-13. Miscellaneous Instruction Execution Times Instruction ANDI to CCR ANDI to SR EORI to CCR EORI to SR EXG EXT LINK MOVE to CCR MOVE to SR MOVE from SR MOVE to USP MOVE from USP NOP ORI to ...
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Address Error Bus Error CHK Instruction Divide by Zero Interrupt ...
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SECTION 8 16-BIT INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock (CLK) periods for the MC68000, MC68HC000, MC68HC001, and the MC68EC000 in 16- bit mode. In this data assumed ...
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Table 8-1. Effective Address Calculation Times Addressing Mode Dn Data Register Direct An Address Register Direct (An) Address Register Indirect (An)+ Address Register Indirect with Postincrement –(An) Address Register Indirect with Predecrement ( An) Address Register Indirect with ...
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Table 8-3. Move Long Instruction Execution Times Source 4(1/0) 4(1/0) An 4(1/0) 4(1/0) (An) 12(3/0) 12(3/0) (An)+ 12(3/0) 12(3/0) –(An) 14(3/0) 14(3/ An) 16(4/0) 16(4/ An, Xn)* 18(4/0) 18(4/0) (xxx).W 16(4/0) ...
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Table 8-4. Standard Instruction Execution Times Instruction ADD/ADDA Byte, Word AND Byte, Word CMP/CMPA Byte, Word DIVS DIVU EOR Byte, Word MULS MULU OR Byte, Word SUB Byte, Word + Add effective address calculation time. † Word or long only ...
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Table 8-5. Immediate Instruction Execution Times Instruction ADDI Byte, Word ADDQ Byte, Word ANDI Byte, Word CMPI Byte, Word EORI Byte, Word MOVEQ ORI Byte, Word SUBI Byte, Word SUBQ Byte, Word 8.5 SINGLE OPERAND INSTRUCTION EXECUTION TIMES Table 8-6 ...
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Table 8-6. Single Operand Instruction Instruction CLR NBCD NEG NEGX NOT Scc TAS TST +Add effective address calculation time. 8.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES Table 8-7 lists the timing data for the shift and rotate instructions. The total number of ...
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BIT MANIPULATION INSTRUCTION EXECUTION TIMES Table 8-8 lists the timing data for the bit manipulation instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described ...
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JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES Table 8-10 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective address (LEA), push effective address (PEA), and move multiple registers (MOVEM) instructions. The total ...
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Table 8-11. Multiprecision Instruction Instruction ADDX CMPM SUBX ABCD SBCD 8.11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES Tables 8-12 and 8-13 list the timing data for miscellaneous instructions. The total number of clock periods, the number of read cycles, and the number ...
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Table 8-12. Miscellaneous Instruction Execution Times Instruction ANDI to CCR ANDI to SR CHK (No Trap) EORI to CCR EORI to SR ORI to CCR ORI to SR MOVE from SR MOVE to CCR MOVE to SR EXG EXT LINK ...
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The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. The number of clock periods, the number of read cycles, and the number ...
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SECTION 9 MC68010 INSTRUCTION EXECUTION TIMES This section contains listings of the instruction execution times in terms of external clock (CLK) periods for the MC68010. In this data assumed that both memory read and write cycles consist of ...
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OPERAND EFFECTIVE ADDRESS CALCULATION TIMES Table 9-1 lists the numbers of clock periods required to compute the effective addresses for instructions. The totals include fetching any extension words, computing the address, and fetching the memory operand. The total number ...
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Table 9-2. Move Byte and Word Instruction Execution Times Source 4(1/0) 4(1/0) An 4(1/0) 4(1/0) (An) 8(2/0) 8(2/0) (An)+ 8(2/0) 8(2/0) –(An) 10(2/0) 10(2/ An) 12(3/0) 12(3/ An, Xn)* 14(3/0) 14(3/0) ...
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Table 9-4. Move Long Instruction Execution Times Source 4(1/0) 4(1/0) An 4(1/0) 4(1/0) (An) 12(3/0) 12(3/0) (An)+ 12(3/0) 12(3/0) –(An) 14(3/0) 14(3/ An) 16(4/0) 16(4/ An, Xn)* 18(4/0) 18(4/0) (xxx).W 16(4/0) ...
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Table 9-6. Standard Instruction Execution Times Instruction ADD/ADDA Byte, Word AND Byte, Word CMP/CMPA Byte, Word DIVS DIVU EOR Byte, Word MULS/MULU OR Byte, Word SUB/SUBA Byte, Word + Add effective address calculation time. * Indicates maximum value. ** Only ...
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IMMEDIATE INSTRUCTION EXECUTION TIMES The numbers of clock periods shown in Table 9-8 include the times to fetch immediate operands, perform the operations, store the results, and read the next operation. The total number of clock periods, the number ...
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Table 9-9. Single Operand Instruction Instruction NBCD NEG NEGX NOT Scc TAS TST +Add effective address calculation time. *Use nonfetching effective address calculation time. Table 9-10. Clear Instruction Execution Times Size Dn CLR Byte, Word 4(1/0) Long 6(1/0) *The size ...
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Table 9-11. Single Operand Instruction Loop Mode Execution Times Loop Continued Valid Count, cc False Instruction Size (An) CLR Byte, 10(0/1) Word Long 14(0/2) NBCD Byte 18(1/1) NEG Byte, 16(1/1) Word Long 24(2/2) NEGX Byte, 16(1/1) Word Long 24(2/2) NOT ...
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Table 9-13. Shift/Rotate Instruction Loop Mode Execution Times Loop Continued Valid Count cc False Instruction Size (An) ASR, ASL Word 18(1/1) LSR, LSL Word 18(1/1) ROR, ROL Word 18(1/1) ROXR, ROXL Word 18(1/1) 9.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES Table ...
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Table 9-15. Conditional Instruction Execution Times Instruction Bcc BRA BSR DBcc 9.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION EXECUTION TIMES Table 9-16 lists the timing data for the jump (JMP), jump to subroutine (JSR), load effective address (LEA), push ...
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The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. The following notation applies in Table 9-17: Dn — Data register ...
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Table 9-18. Miscellaneous Instruction Execution Times Instruction Size ANDI to CCR — ANDI to SR — CHK — EORI to CCR — EORI to SR — EXG — EXT Word Long LINK — MOVE from CCR — MOVE to CCR ...
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EXCEPTION PROCESSING EXECUTION TIMES Table 9-19 lists the timing data for exception processing. The numbers of clock periods include the times for all stacking, the vector fetch, and the fetch of the first instruction of the handler routine. The ...
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SECTION 10 ELECTRICAL AND THERMAL CHARACTERISTICS This section provides information on the maximum rating and thermal characteristics for the MC68000, MC68HC000, MC68HC001, MC68EC000, MC68008, and MC68010. 10.1 MAXIMUM RATINGS Rating Supply Voltage Input Voltage Maximum Operating Temperature Range Commerical Extended ...
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POWER CONSIDERATIONS The average die-junction temperature can be obtained from +(P D • where Ambient Temperature Package Thermal Resistance, ...
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Table 10-1 summarizes maximum power dissipation and average junction temperature for the curve drawn in Figure 10-1, using the minimum and maximum values of ambient temperature for different packages and substituting J C for J A (assuming good thermal management). ...
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Table 10-1. Power Dissipation and Junction Temperature vs Temperature Package T A Range ...
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P-channel transistor. Also, since only one transistor is turned on during the steady state, power consumption is determined by leakage currents. Because the basic CMOS cell is composed of two complementary transistors, a virtual semiconductor ...
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BCLK DRIVE TO 0.5 V VALID OUTPUTS(1) OUTPUT n DRIVE TO INPUTS(2) DRIVE TO RSTI (3) NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This input timing is ...
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MC68000/68008/68010 DC ELECTRICAL CHARACTERISTICS (V CC =5.0 VDC 5%; GND=0 VDC Characteristic Input High Voltage Input Low Voltage Input Leakage Current BERR , BGACK DTACK, CLK, IPL0—IPL2, VPA @ ...
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DC ELECTRICAL CHARACTERISTICS (Applies To All Processors Except The MC68EC000) H Characteristic Input High Voltage Input Low Voltage Input Leakage Current BERR , BGACK DTACK, CLK, IPL0—IPL2, VPA @ 5.25 V Three-State (Off State) ...
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MC68008 AC ELECTRICAL SPECIFICATIONS — CLOCK TIMING Figure 10-3) Num Characteristic Frequency of Operation 1 Cycle Time 2,3 Clock Pulse Width 4,5 Clock Rise and Fall Times *These specifications represent an improvement over previously published specifications for the 8-, ...
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AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (V CC =5.0 VDC 5+; GND (see Figures 10-4 and 10-5) (Applies To All Processors Except The MC68EC000) Num Characteristic 6 Clock ...
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Num Characteristic 2 26 Data-Out Valid to DS Asserted (Write Data-In Valid to Clock Low (Setup Time on Read) 5 27A Late BERR Asserted to Clock Low (setup Time AS, DS Negated to DTACK Negated (Asynchronous ...
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Num Characteristic 5 47 Asynchronous Input Setup Time BERR Asserted to DTACK Asserted 2,3,5 48 DTACK Asserted to BERR Asserted (MC68010 Only AS, DS, Negated to E Low 50 E Width High 51 E ...
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S0 CLK FC2–FC0 A23– LDS / UDS 17 R/W DTACK DATA IN BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their ...
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S0 CLK FC2-FC0 A23- LDS / UDS R/W DTACK DATA OUT BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Timing measurements are referenced to and from a low voltage of 0.8 V ...
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AC ELECTRICAL SPECIFICATIONS—MC68000 TO M6800 PERIPHERAL (V CC (Applies To All Processors Except The MC68EC000) Num Characteristic 12 1 Clock Low to AS, DS Negated 18 1 Clock High to R/W High (Read Clock High to R/W ...
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CLK A23- R VPA VMA DATA OUT DATA IN NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows ...
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AC ELECTRICAL SPECIFICATIONS — BUS ARBITRATION VDC 5%; GND=0 VDC See Figure s 10-7 – 10-11) (Applies To All Processors Except The MC68EC000) Num Characteristic 7 Clock High to Address, Data ...
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STROBES AND R/W BR BGACK CLK NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, IPL2-IPL0, and VPA guarantees their recognition at the next falling edge of the clock. Figure 10-7. ...
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CLK BGACK AS DS VMA R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure ...
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CLK BGACK AS DS VMA R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure ...
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CLK BGACK AS DS VMA R/W FC2-FC0 A19-A0 D7-D0 NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version Only. ...
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CLK BGACK AS DS VMA R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure ...
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MC68EC000 DC ELECTRICAL SPECIFICATIONS GND=0 VDC Characteristic Input High Voltage Input Low Voltage Input Leakage Current BERR DTACK , CLK, IPL2–IPL0, AVEC @5.25 V Three-State (Off State) Input Current @2.4 ...
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MC68EC000 AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES 10-12 and 10-13) Num Characteristic 6 Clock Low to Address Valid 6A Clock High to FC Valid 7 Clock High to Address, Data Bus High Impedance (Maximum) 8 Clock High ...
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Num Characteristic 29 AS, DS Negated to Data-In Invalid (Hold Time on Read) 29A AS, DS Negated to Data-In High Impedance 30 AS, DS Negated to BERR Negated DTACK Asserted to Data-In Valid (Setup Time) 32 ...
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S0 CLK FC2–FC0 A23– LDS / UDS 17 R/W DTACK DATA IN BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their ...
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CLK FC2-FC0 A23-A0 AS LDS / UDS R/W DTACK DATA OUT BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Timing measurements are referenced to and from a low voltage of 0.8 V and a ...
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MC68EC000 AC ELECTRICAL SPECIFICATIONS—BUS ARBITRATION (VCC=5.0VDC Num Characteristic 7 Clock High to Address, Data Bus High Impedance (Maximum) 16 Clock High to Control Bus High Impedance 33 Clock High to BG Asserted 34 Clock High to BG Negated 35 ...
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CLK R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. Figure 10-14. MC68EC000 Bus Arbitration Timing Diagram MOTOROLA ...
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SECTION 11 ORDERING INFORMATION AND MECHANICAL DATA This section provides pin assignments and package dimensions for the devices described in this manual. 11.1 PIN ASSIGNMENTS Package 64-Pin Dual-In-Line 68-Terminal Pin Grid Array 64-Lead Quad Pack 68-Lead Quad Flat Pack 52-Lead ...
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DTACK BGACK RESET 11-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL UDS 7 LDS CLK MC68000 MC68010 ...
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MC68000/MC68010/MC68HC000 K NC FC2 FC0 BERR IPL0 FC1 IPL2 IPL1 G VMA VPA F (BOTTOM VIEW) HALT RESET E CLK GND BGACK BG R/W B DTACK ...
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DTACK BG BGACK CLK GND GND 18 NC HALT RESET VMA E VPA BERR IPL2 IPL1 R/W DTACK BG BGACK CLK GND GND MODE HALT RESET NC AVEC BERR IPL2 IPL1 Figure 11-3. 68-Lead ...
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DTACK BG BGACK CLK GND GND MODE HALT RESET VMA E VPA BERR IPL2 IPL1 Figure 11-3. 68-Lead Quad Pack ( A10 A11 A12 A13 A 21 A14 CC V A15 GND A16 A17 ...
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A10 A11 A12 A13 A14 V A15 GND A16 A17 A18 A19 11-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...
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R/W DTACK CLK GND MODE HALT RESET AVEC BERR IPL2 IPL1 IPL0 FC2 Figure 11-6. 64-Lead Quad Flat Pack 11.2 PACKAGE DIMENSIONS Case Package 740-03 L Suffix 767-02 P Suffix 746-01 LC Suffix 754-01 R and ...
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F D NOTES: 1. DIMENSION -A- IS DATUM. 2. POSTIONAL TOLERANCE FOR LEADS: 0.25 (0.010 -T- IS SEATING PLANE 4. DIMENSION "L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 5. DIMENSIONING AND TOLERANCING ...
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NOTES: 1. -R- IS END OF PACKAGE DATUM PLANE -T- IS BOTH A DATUM AND SEATING PLANE 2. POSITIONAL TOLERANCE FOR LEADS 1 AND 48. 0.51 (0.020 POSITIONAL TOLERANCE FOR LEAD ...
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F D NOTES: 1. DIMENSION -A- IS DATUM. 2. POSTIONAL TOLERANCE FOR LEADS: 0.25 (0.010 -T- IS SEATING PLANE 4. DIMENSION "L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 5. DIMENSIONING AND TOLERANCING ...
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F D NOTES: 1. DIMENSIONS A AND B ARE DATUMS. 2. -T- IS SEATING PLANE. 3. POSITIONAL TOLERANCE FOR LEADS (DIMENSION D): 0.25 (0.010 DIMENSION B DOES NOT INCLUDEMOLD FLASH. 5. ...
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Figure 11-11. Case 765A-05—RC Suffix 11-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...
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APPENDIX A MC68010 LOOP MODE OPERATION In the loop mode of the MC68010, a single instruction is executed repeatedly under control of the test condition, decrement, and branch (DBcc) instruction without any instruction fetch bus cycles. The execution of a ...
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Fetch the MOVE instruction. 2. Fetch the DBEQ instruction. 3. Read the operand at the address in A0. 4. Write the operand at the address in A1. 5. Fetch the displacement word of the DBEQ instruction. Of these five ...
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Table A-1. MC68010 Loop Mode Instructions Opcodes MOVE [BWL] ADD [BWL] AND [BWL] CMP [BWL] OR [BWL] SUB [BWL] ADDA [WL] CMPA [WL] SUBA [WL] ADD [BWL] AND [BWL] EOR [BWL] OR [BWL] SUB [BWL] ABCD [B] ADDX [BWL] SBCD ...