MC68306EH16B Freescale Semiconductor, MC68306EH16B Datasheet - Page 127

• Manufacturer Part Number: MC68306EH16B
• Description: IC MPU INTEGRATED 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68306EH16B

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 16.7MHz
• No. Of Timers: 1
• Embedded Interface Type: UART
• Digital Ic Case Style: PQFP
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

channel A mode register pointer points to DUMR1. The pointer is set to DUMR1 by
RESET or by a set pointer command, using control register A. After reading or writing
DUMR1A, the pointer points to DUMR2A.
RxRTS—Receiver Request-to-Send Control
RxIRQ—Receiver Interrupt Select
ERR—Error Mode
PM1–PM0—Parity Mode
MOTOROLA
This feature can be used for flow control to prevent overrun in the receiver by using the
RTS≈ output to control the CTS≈ input of the transmitting device. If both the receiver and
transmitter are programmed for RTS control, RTS control will be disabled for both since
this configuration is incorrect. See 6.4.1.17 Mode Register 2 for information on
programming the transmitter RTS≈ control.
This bit controls the meaning of the three FIFO status bits (RB, FE, and PE) in the
DUSR for the channel.
These bits encode the type of parity used for the channel (see Table 6-1). The parity bit
is added to the transmitted character, and the receiver performs a parity check on
incoming data. These bits can alternatively select multidrop mode for the channel.
1 = Upon receipt of a valid start bit, RTS≈ is negated if the channel's FIFO is full.
0 = The receiver has no effect on RTS≈.
1 = FFULL is the source that generates IRQ.
0 = RxRDY is the source that generates IRQ.
1 = Block mode—The values in the channel DUSR are the accumulation (i.e., the
0 = Character mode—The values in the channel DUSR reflect the status of the
RTS≈ is reasserted when the FIFO has an empty position available.
logical OR) of the status for all characters coming to the top of the FIFO since the
last reset error status command for the channel was issued. Refer to 6.4.1.5
Command Register (DUCR) for more information on serial module commands.
character at the top of the FIFO.
ERR = 0 must be used to get the correct A/D flag information
when in multidrop mode.
DUMR1A, DUMR1B
Read/Write
RESET:
RxRTS
Freescale Semiconductor, Inc.
7
0
For More Information On This Product,
RxIRQ
6
0
MC68306 USER'S MANUAL
Go to: www.freescale.com
ERR
5
0
PM1
4
0
NOTE
PM0
3
0
PT
2
0
B/C1
1
0
B/C0
0
0
6-19