MPC870CZT66 Freescale Semiconductor, MPC870CZT66 Datasheet - Page 2
![IC MPU POWERQUICC 66MHZ 256PBGA](/photos/6/79/67915/mpc870czt66_sml.jpg)
MPC870CZT66
Manufacturer Part Number
MPC870CZT66
Description
IC MPU POWERQUICC 66MHZ 256PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC870VR80.pdf
(84 pages)
Specifications of MPC870CZT66
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
66MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC870CZT66
Manufacturer:
MOT
Quantity:
12 388
Company:
Part Number:
MPC870CZT66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Overview
1
The MPC875/MPC870 is a versatile single-chip integrated microprocessor and peripheral combination
that can be used in a variety of controller applications and communications and networking systems. The
MPC875/MPC870 provides enhanced ATM functionality over that of other ATM-enabled members of the
MPC860 family.
Table 1
2
The MPC875/MPC870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx
core, a system integration unit (SIU), and a communications processor module (CPM).
The following list summarizes the key MPC875/MPC870 features:
2
•
•
•
•
Overview
Features
Embedded MPC8xx core up to 133 MHz
Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes
Single-issue, 32-bit core (compatible with the Power Architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional
— 8-Kbyte data cache and 8-Kbyte instruction cache (see
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
— Advanced on-chip emulation debug mode
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
shows the functionality supported by the MPC875/MPC870.
MPC875
MPC870
execution
– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
– Caches are physically addressed, implement a least recently used (LRU) replacement
spaces and 16 protection groups
Part
cache blocks
algorithm, and are lockable on a cache block basis
MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4
I Cache
Cache (Kbytes)
8
8
D Cache
Table 1. MPC875/MPC870 Devices
8
8
10BaseT
—
1
Ethernet
10/100
2
2
Table
SCC
—
1
1)
SMC
1
1
USB
1
1
Freescale Semiconductor
Security
Engine
Yes
No