MPC850DEVR50BU Freescale Semiconductor, MPC850DEVR50BU Datasheet - Page 52

• Manufacturer Part Number: MPC850DEVR50BU
• Description: IC MPU PWRQUICC 50MHZ 256-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC Ir

Specifications of MPC850DEVR50BU

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: BGA
• Core Size: 32 Bit
• Program Memory Size: 3KB
• Cpu Speed: 50MHz
• Embedded Interface Type: I2C, RS232, SPI, TDM, USB, UTOPIA
• Digital Ic Case Style: BGA
• No. Of Pins: 256
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPM Electrical Characteristics
8.6
Table 18
Table 19
52
1
2
1
2
The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as an external sync signal.
Num
Num
100
102
103
104
105
106
107
108
100
101
102
103
104
105
106
107
108
The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1.
Also applies to CD and CTS hold time when they are used as an external sync signals.
provides the NMSI external clock timing.
provides the NMSI internal clock timing.
SCC in NMSI Mode Electrical Specifications
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
RCLKx and TCLKx frequency
RCLKx and TCLKx rise/fall time
TXDx active delay (from TCLKx falling edge)
RTSx active/inactive delay (from TCLKx falling edge)
CTSx setup time to TCLKx rising edge
RXDx setup time to RCLKx rising edge
RXDx hold time from RCLKx rising edge
CDx setup time to RCLKx rising edge
RCLKx and TCLKx frequency
table)
RCLKx and TCLKx width low
RCLKx and TCLKx rise/fall time
TXDx active delay (from TCLKx falling edge)
RTSx active/inactive delay (from TCLKx falling edge)
CTSx setup time to TCLKx rising edge
RXDx setup time to RCLKx rising edge
RXDx hold time from RCLKx rising edge
CDx setup time to RCLKx rising edge
Table 18. NMSI External Clock Timing
Characteristic
Table 19. NMSI Internal Clock Timing
Characteristic
1
(x = 2, 3 for all specs in this table)
1
(x = 2, 3 for all specs in this
2
2
1/SYNCCLK +5
1/SYNCCLK
40.00
40.00
40.00
0.00
0.00
0.00
0.00
Min
—
All Frequencies
All Frequencies
0.00
0.00
5.00
5.00
5.00
5.00
Min
—
SYNCCLK/3
30.00
30.00
Max
—
—
—
—
—
Freescale Semiconductor
15.00
50.00
50.00
Max
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
Unit