SPC5200CVR400B Freescale Semiconductor, SPC5200CVR400B Datasheet - Page 22

• Manufacturer Part Number: SPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of SPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Core Size: 32 Bit
• No. Of I/o's: 56
• Program Memory Size: 32KB
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SCI, SPI, USB
• Digital Ic Case Style: BGA
• Rohs Compliant: Yes
• Family Name: MPC52xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

NOTES:
1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
NOTES:
1. See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven signal transitions drive
22
upon whether the clock frequency is above 33 MHz.
peak-to-peak portion of the clock waveform as shown in
to their Voh or Vol level within one Tcyc.
t
t
val
su
Sym
t
t
t
t
(ptp) Input Setup Time to CLK — point
t
Sym
val
(ptp)
on
off
t
su
t
t
h
high
—
—
cyc
low
CLK to Signal Valid Delay —
CLK to Signal Valid Delay —
Input Setup Time to CLK —
Input Hold Time from CLK
Float to Active Delay
Active to Float Delay
PCI CLK Cycle Time
PCI CLK High Time
PCI CLK Slew Rate
PCI CLK Low Time
bused signals
bused signals
point to point
PCI Clock Jitter
Description
(peak to peak)
PCI CLK
Description
to point
0.3 Vcc
0.4 Vcc
0.5 Vcc
Table 22. PCI CLK Specifications
Table 23. PCI Timing Parameters
Figure 9. PCI CLK Waveform
MPC5200B Data Sheet, Rev. 4
Min
2
2
2
3
5
0
Min
0.6 Vcc
1.5
15
—
6
6
t
66 MHz
high
66 MHz
Figure
t
Max
cyc
14
—
—
—
—
Max
6
6
200
30
—
—
4
9.
0.2 Vcc
t
low
10,12
Min
2
2
2
7
0
Min
30
11
11
—
1
33 MHz
33 MHz
Max
11
12
28
—
—
—
—
Max
200
0.4 Vcc, p-to-p
—
—
—
4
(minimum)
Units
Units
V/ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
Notes
(1),(3)
(1),(2),(3)
(1),(2),(3)
Notes
—
—
(2)
—
(3),(4)
(3),(4)
(1)
(1)
(4)
SpecID
A6.1
A6.2
A6.3
A6.4
SpecID
A6.10
A6.11
—
A6.5
A6.6
A6.7
A6.8
A6.9