IP80C88-2 Intersil, IP80C88-2 Datasheet - Page 6

• Manufacturer Part Number: IP80C88-2
• Description: IC CPU 8/16BIT 5V 8MHZ 40-DIP
• Manufacturer: Intersil

Specifications of IP80C88-2

• Processor Type: 80C88 8/16-Bit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Pin Description
The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which
are unique to the maximum mode are described; all other pin functions are as described above.
MAXIMUM MODE SYSTEM (i.e., MN/MX = GND).
SYMBOL
RQ/GT0,
RQ/GT1
LOCK
S0
S1
S2
NUMBER
PIN
26
27
28
31
30
29
(Continued)
TYPE
I/O
O
O
O
O
6
STATUS: is active during clock high of T4, T1 and T2,
and is returned to the passive state (1, 1, 1) during T3 or
during Tw when READY is HIGH. This status is used by
the 82C88 bus controller to generate all memory and I/O
access control signals. Any change by S2, S1 or S0
during T4 is used to indicate the beginning of a bus
cycle, and the return to the passive state in T3 or Tw is
used to indicate the end of a bus cycle.
These signals are held at a high impedance logic one
state during “grant sequence”.
REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local
bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 having higher
priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may be left unconnected.
The request/grant sequence is as follows (see RQ/GT Timing Sequence):
Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK
cycle after bus exchange. Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4
of the cycle when all the following conjugations are met:
If the local bus is idle when the request is made the two possible events will follow:
LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is
active (LOW). The LOCK signal is activated by the “LOCK” prefix instruction and remains active until the
completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one
state during “grant sequence”. In Max Mode, LOCK is automatically generated during T2 of the first INTA
cycle and removed during T2 of the second INTA cycle.
1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to the
2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master (pulse
3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold”
1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply
80C88 (pulse 1).
2), indicates that the 80C88 has allowed the local bus to float and that it will enter the “grant sequence”
state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during
“grant sequence”.
request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU then
enters T4 (or T1 if no bus cycles pending).
with condition number 1 already satisfied.
80C88
DESCRIPTION
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
CHARACTERISTICS
February 22, 2008
FN2949.4