A80960KB20 Intel, A80960KB20 Datasheet - Page 8

• Manufacturer Part Number: A80960KB20
• Description: IC MPU I960KB 20MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80960KB20

• Processor Type: i960
• Features: KB suffix, 32-Bit, 512 Byte Cache
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803516

80960KB
1.1
The 80960 architecture is based on the most recent
advances in microprocessor technology and is
grounded in Intel’s long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960KB’s exceptional
performance:
2
1. Large Register Set. Having a large number of
2. Fast Instruction Execution. Simple functions
3. Load/Store Architecture. One way to improve
4. Simple Instruction Formats. All instructions
5. Overlapped Instruction Execution. Load
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexi-
bility, the 80960KB provides thirty-two 32-bit
registers and four 80-bit floating point registers.
(See Figure 2.)
make up the bulk of instructions in most
programs so that execution speed can be
improved by ensuring that these core instruc-
tions are executed as quickly as possible. The
most frequently executed instructions such as
register-register moves, add/subtract, logical
operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)
execution speed is to reduce the number of
times that the processor must access memory
to perform an operation. As with other
processors based on RISC technology, the
80960KB has a Load/Store architecture. As
such, only the LOAD and STORE instructions
reference
operate on registers. This type of architecture
simplifies instruction decoding and is used in
combination with other techniques to increase
parallelism.
in the 80960KB are 32 bits long and must be
aligned on word boundaries. This alignment
makes it possible to eliminate the instruction
alignment stage in the pipeline. To simplify the
instruction
instruction formats; each instruction uses only
one format. (See Figure 3.)
operations allow execution of subsequent
instructions to continue before the data has
been returned from memory, so that these
instructions
80960KB manages this process transparently
Key Performance Features
memory;
decoder,
can
overlap
all
there
other
the
are
instructions
load.
only
The
five
6. Integer Execution Optimization. When the
7. Bandwidth Optimizations. The 80960KB gets
8. Cache Bypass. If a cache miss occurs, the
to software through the use of a register score-
board. Conditional instructions also make use
of a scoreboard so that subsequent unrelated
instructions may be executed while the condi-
tional instruction is pending.
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value
is sent immediately to its destination register.
Yet at the same time, the value is put on a
bypass path to the ALU, thereby saving the
time that otherwise would be required to
retrieve the value for the next operation.
optimal use of its memory bus bandwidth
because the bus is tuned for use with the
on-chip instruction cache: instruction cache
line size matches the maximum burst size for
instruction fetches. The 80960KB automatically
fetches four words in a burst and stores them
directly in the cache. Due to the size of the
cache and the fact that it is continually filled in
anticipation of needed instructions in the
program flow, the 80960KB is relatively insen-
sitive to memory wait states. The benefit is that
the 80960KB delivers outstanding performance
even with a low cost memory system.
processor fetches the needed instruction then
sends it on to the instruction decoder at the
same time it updates the cache. Thus, no extra
time is spent to load and read the cache.