MPC8358EZQAGDGA Freescale Semiconductor, MPC8358EZQAGDGA Datasheet - Page 23

• Manufacturer Part Number: MPC8358EZQAGDGA
• Description: MPU POWERQUICC II PRO 668-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8358EZQAGDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 668-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 6
Freescale Semiconductor
At recommended operating conditions with GV
MDQS epilogue end
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in ¼ applied cycle increments through the clock control register.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
5. Note that t
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that t
8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
For the skew measurements referenced for t
address/command valid with the rising edge of MCK.
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
½ applied cycle.
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same
delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. See the MPC8360E PowerQUICC II Pro Integrated
Communications Processor Family Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.
conventions described in note 1.
DDKHAS
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
shows the DDR SDRAM output timing for address skew with respect to any MCK.
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
follows the symbol conventions described in note 1. For example, t
Parameter
Figure 6. Timing Diagram for t
8
ADDR/CMD
ADDR/CMD
MCK[n]
MCK[n]
DD
Synchronous Mode (continued)
of (1.8 V or 2.5 V) ± 5%.
DDKLDX
AOSKEW
MCK
symbolizes DDR timing (DD) for the time t
it is assumed that the clock adjustment is set to align the
memory clock reference (K) goes from the high (H) state until outputs
Symbol
t
DDKHME
t
AOSKEW(min)
CMD
t
AOSKEW(max)
1
CMD
t
(first two letters of functional block)(signal)(state)(reference)(state)
MCK
for outputs. Output hold time can be read as DDR timing
AOSKEW
–0.6
Min
Measurement
NOOP
NOOP
DDKHMH
DDKHMH
can be modified through control
DDKHMP
describes the DDR timing (DD)
Max
MCK
0.9
memory clock reference
follows the symbol
DDR and DDR2 SDRAM
Unit
ns
Notes
for
7
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