MPC8347EVVALFB Freescale Semiconductor, MPC8347EVVALFB Datasheet - Page 36

• Manufacturer Part Number: MPC8347EVVALFB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347EVVALFB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.36V
• Operating Supply Voltage (min): 1.24V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Local Bus
36
Output hold from local bus clock for LAD/LDP
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols for timing specifications follow the pattern of t
2. All timings are in reference to the rising edge of LSYNC_IN.
3. All signals are measured from OV
4. Input timings are measured at the pin.
5. t
6. t
7. t
8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
Local bus cycle time
Input setup to local bus clock
Input hold from local bus clock
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
and t
for the input (I) to go invalid (X) with respect to the time the t
(1). Also, t
(O) going invalid (X) or output hold time.
signaling levels.
the load on the LAD output pins.
load on the LAD output pins.
output pins.
component pin is less than or equal to that of the leakage current specification.
LBOTOT1
LBOTOT2
LBOTOT3
(first two letters of functional block)(reference)(state)(signal)(state)
should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than
should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the
should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD
LBKHOX
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
symbolizes local bus timing (LB) for the t
Table 34. Local Bus General Timing Parameters—DLL On (continued)
Table 35. Local Bus General Timing Parameters—DLL Bypass
Parameter
Parameter
DD
/2 of the rising edge of LSYNC_IN to 0.4 × OV
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
LBK
LBK
clock reference (K) to go high (H), with respect to the output
clock reference (K) goes high (H), in this case for clock one
Symbol
Symbol
t
t
t
t
t
LBKHOX2
LBOTOT1
LBOTOT2
LBOTOT3
t
t
LBKHOZ
LBIVKH
LBIXKH
t
LBK
1
1
Min
Min
1.0
1.5
2.5
15
—
1
7
3
DD
LBIXKH1
of the signal in question for 3.3 V
symbolizes local bus timing (LB)
Max
Max
3.8
—
—
—
—
—
—
—
9
Freescale Semiconductor
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
for inputs
Notes
Notes
3, 4
3, 4
3
8
6
2
5
7