MC68LC040RC40A Freescale Semiconductor, MC68LC040RC40A Datasheet - Page 217

• Manufacturer Part Number: MC68LC040RC40A
• Description: IC MPU 32BIT 40MHZ 179-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC040RC40A

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
The third step is to save the current processor contents for all exceptions other than reset.
The processor creates one of five exception stack frame formats on the active supervisor
stack and fills it with information appropriate for the type of exception. Other information
can also be stacked, depending on which exception is being processed and the state of
the processor prior to the exception. If the exception is an interrupt and the M-bit of the
SR is set, the processor clears the M-bit and builds a second stack frame on the interrupt
stack. Figure 8-2 illustrates the general form of the exception stack frame.
15
12
0
SP
STATUS REGISTER
PROGRAM COUNTER
FORMAT
VECTOR OFFSET
ADDITIONAL PROCESSOR STATE INFORMATION
(2 OR 26 WORDS, IF NEEDED)
Figure 8-2. General Form of Exception Stack Frame
The last step initiates execution of the exception handler. The processor multiplies the
vector number by four to determine the exception vector offset. It adds the offset to the
value stored in the vector base register (VBR) to obtain the memory address of the
exception vector. Next, the processor loads the program counter (PC) (and the interrupt
stack pointer (ISP) for the reset exception) from the exception vector table entry. After
prefetching the first four long words to fill the instruction pipe, the processor resumes
normal processing at the address in the PC. When the processor executes an RTE
instruction, it examines the stack frame on top of the active supervisor stack to determine
if it is a valid frame and what type of context restoration it requires.
All exception vectors are located in the supervisor address space and are accessed using
data references. Only the initial reset vector is fixed in the processor’s memory map; once
initialization is complete, there are no fixed assignments. Since the VBR provides the base
address of the exception vector table, the exception vector table can be located anywhere
in memory; it can even be dynamically relocated for each task that an operating system
executes.
The M68040 supports a 1024-byte vector table containing 256 exception vectors (see
Table 8-1). Motorola defines the first 64 vectors and reserves the other 192 vectors for
user-defined interrupt vectors. External devices can use vectors reserved for internal
purposes at the discretion of the system designer. External devices can also supply vector
numbers for some exceptions. External devices that cannot supply vector numbers use
the autovector capability, which allows the M68040 to automatically generate a vector
number.
8-4
M68040 USER’S MANUAL
MOTOROLA
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