MC68040RC33V Freescale Semiconductor, MC68040RC33V Datasheet - Page 189

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MC68040RC33V

Manufacturer Part Number
MC68040RC33V
Description
IC MICROPROCESSOR 32BIT PGA-182
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040RC33V

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
182
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

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MOTOROLA
*BG
BBI
IBR
BCLK
IBR
BBO
D
Figure 7-30. M68040 Internal Interpretation State Diagram and
BBO DRIVEN BY
THREE-STATED
OWNERSHIP,
*ENDCYCLE
MC68040,
IMPLICIT
Q
BG
BBI
*BG
BBI
BR
BB
Freescale Semiconductor, Inc.
For More Information On This Product,
IBR
*BG
BG*
TSI
External Bus Arbiter Circuit
IBR
*BG
IBR
Go to: www.freescale.com
M68040 USER’S MANUAL
TSI
*BBI
ENDCYCLE
*THREE-STATED
BBO DRIVEN BY
*THREE-STATED
BBO DRIVEN BY
MC68040,
MC68040,
SNOOP,
IDLE,
IBR
BBI
TSI
ENDCYCLE
*
BG
BBI
TSI
*BG
= Internal bus request signal (see schematic below).
= Bus busy driven by alternate bus master.
= Transfer start as an input, sampled by the MC68040.
= Whatever terminates a bus transaction
= The 040 may or may not transition if an active bus
= Indicates the signal is asserted for that device.
*BG
whether it is normal, bus error, or retried. Note
that false burst cycles are treated as a line
transaction. False locked transactions
are treated the same as any other bus cycle.
cycle is terminated with a bus error, and BG is
asserted.
*TSI
*IBR
*ENDCYCLE
BBI
TSI
BG
*BBO DRIVEN BY
PROTOCOL
VIOLATION
THREE-STATED
TIP
OWN/PARK,
BBI
MC68040,
BG
*BG
*ENDCYCLE
*IBR
BG
ENDCYCLE
*BG
*TIP
TIP*
7- 47

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