XS1-L01A-TQ128-C4 XMOS, XS1-L01A-TQ128-C4 Datasheet - Page 11
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XS1-L01A-TQ128-C4
Manufacturer Part Number
XS1-L01A-TQ128-C4
Description
IC MPU 32BIT SINGLE CORE 128TQFP
Manufacturer
XMOS
Datasheet
1.XS1-L01A-TQ128-C5.pdf
(26 pages)
Specifications of XS1-L01A-TQ128-C4
Processor Type
XCore 32-Bit
Speed
400MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
128-TQFP Exposed Pad, 128-eTQFP, 128-HTQFP, 128-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1002
XS1-L01-TQ128-C4
XS1-L01-TQ128-C4
Available stocks
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Part Number
Manufacturer
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XS1-L1 128TQFP Datasheet (2.2)
The XS1-L1 device contains a standard 5 pin JTAG interface, which allows the following
The JTAG interface on the XS1-L1 consists of the following signals:
The TRST_N pin must be driven low for at least 100ns after the power supplies are
3.5 One Time Programmable Memory
Functional description
OTP_VDDIO OTP Power Supply. Must be 3V3. This supply must be at its nominal
OTP_VPP OTP Programming Voltage (can be used for faster program times otherwise
3.6 JTAG Operation
functionality:
stable to reset the JTAG circuitry. If JTAG debug is not required, the TRST_N pin can
be tied to ground to hold the JTAG port in reset.
Each XS1-L device contains multiple TAP controllers, each enabling different func-
tionality. Directly after reset, two TAP controllers are present in the JTAG chain - the
boundary scan TAP (BS TAP) and the chip TAP (CHIP TAP).
Signal
OTP_VDDIO
OTP_VPP
Signal
TCK
TMS
TRST_N
TDI
TDO
level before the core supply is enabled.
internal charge pump is used). Nom 6.5V if used.
Boundary scan testing for verifying printed circuit board connectivity.
In-circuit source level debugging of the XCore.
Programming of the One Time Programmable (OTP) ROM.
Pin ID
45
46
Pin ID
61
58
56
62
63
I/O
I, PU, ST
I, PU, ST
I, PU, ST
I, PU, ST
OT, PD
I/O
pwr
pwr
Description
OTP Power Supply
OTP Programming Voltage
Description
Test clock
Test mode select
Test reset (active low)
Test data in
Test data out
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