XS1-L02A-QF124-I5 XMOS, XS1-L02A-QF124-I5 Datasheet - Page 9

• Manufacturer Part Number: XS1-L02A-QF124-I5
• Description: IC MPU 32BIT DUAL CORE 124QFN
• Manufacturer: XMOS

Specifications of XS1-L02A-QF124-I5

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 124-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1031

XS1-L2 124QFN Datasheet (1.5)
To boot the master core on the XS1-L2 device from an SPI interface, the SPI device
Bits [1:0] control the PLL boot mode according to the following table:
NOTE: If secure boot from OTP is enabled by programming the OTP, the boot mode
indicated on the MODE[4:2] pins is ignored. For further details on booting XCores
see the
MODE[4] Tie low for normal use. If this pin is asserted high, the second core may
DEBUG This pin is used to synchronize the debugging of multiple XS1 devices. This
RST_N Active low asynchronous-assertion reset signal. This pin must be driven
3.3 SPI Interface
must be connected as follows:
MODE4
X
X
0
0
1
1
MODE1
0
0
1
1
be booted from an SPI flash device.
pin can operate in both output and input mode. In output mode and when
configured to do so, DEBUG is driven low by the device when one or more
internal XCore processors hit a debug break point. Prior to this point the pin
will be tri-stated. In input mode and when configured to do so, driving this pin
low will put all internal CPUs into debug mode. Software can set the behavior
of each internal XCore based on this pin. This pin should have an external pull
up of 4K7 ohms.
low for at least 100ns to reset the entire device. Following a reset the PLL
re-establishes lock after which the XCores boot up according to the boot mode
(see MODE).
XS1-L System
MODE3
0
0
1
1
1
1
MODE0
0
1
0
1
Specification.
MODE2
0
1
0
1
0
1
PLL Multiplier Ratio
30.75
4
8.3333
20
www.xmos.com
Boot Mode
None - Both cores wait to be booted (via JTAG)
Reserved
Master core boots from XMOS Link B, slave core
boots from internal link via master core
Master core boots from SPI, slave core boots from
internal link via master core
Reserved
Both cores boot from SPI independantly
PLL reference clk
4.22 to 13 MHz
21.66 to 100 MHz
10.4 to 48 MHz
4.33 to 20 MHz
Boot Frequency
130 to 399.75 MHz
86.66 to 400 MHz
86.66 to 400 MHz
86.66 to 400 MHz
9/28