XS1-G04B-FB512-I4 XMOS, XS1-G04B-FB512-I4 Datasheet - Page 11
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XS1-G04B-FB512-I4
Manufacturer Part Number
XS1-G04B-FB512-I4
Description
IC MPU 32BIT QUAD CORE 512FBGA
Manufacturer
XMOS
Datasheet
1.XS1-G04B-FB512-C4.pdf
(30 pages)
Specifications of XS1-G04B-FB512-I4
Processor Type
XCore 32-Bit
Speed
1600MIPS
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
512-BGA
For Use With
XMOS AVB REF KIT - KIT REF AVB W/4 XS1-G-DK880-1016 - KIT REF LED RGB 16X32 W/XC-3880-1015 - BOARD KIT XS1-G4 LED CTRL TILE880-1014 - BOARD DEV KIT XS1-G4 ETHERNET880-1013 - BOARD DEV KIT XS1-G4880-1012 - KIT DEV 4CORE G4 W/LCD TOUCH
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1011
Available stocks
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XS1-G4 512BGA Datasheet (3.5)
SS_DEBUG This pin is used to synchronize the debugging of multiple G4 devices.
SS_RESET Active low asynchronous-assertion reset signal. At power-up, this pin
SS_XC0_CFG0 Reserved, tie pin to IO_VDD
SS_TEST_ENA Reserved, tie pin to ground.
SS_RESERVED Reserved, leave unconnected.
NOTE: If secure boot from OTP is enabled by programming the OTP, the boot
mode indicated on the XC0_BS[1:0] and XC1_BS[1:0] pins is ignored.
After reset is complete, bits 2:0 become outputs and indicate the XCore0 or
XCore1 boot mode. Bit 3 indicates boot has completed. Codes for bits 2:0 are:
For further details on booting XCores see the XS1-G System Specification
document (http://xmos.com/published/xsystem).
This pin can operate in both output and input mode. In output mode and when
configured to do so, SS_DEBUG is driven low by the device when one or more
internal XCore processors hit a debug break point. Prior to this point the pin is
tri-stated. In input mode and when configured to do so, driving this pin low
puts all internal CPUs into debug mode. Software can set the behavior of each
internal XCore based on this pin. This pin should have an external pull up to
IO_VDD(3.3V) of 4K7 ohms.
must be activated for at least 5us after the power supplies are stable to ensure
reliable boot up. Following a reset the PLL re-establishes lock after which the
XCores boot up according to the BOOT_MODE (see SS_XC0_BS1, SS_XC0_BS0).
Value
001
010
011
100
101
www.xmos.com
Description
Boot from OTP
Reserved
Reserved
Boot from SPI
Boot from JTAG
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